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PDF AMD-K6-2E Data sheet ( Hoja de datos )
| Número de pieza | AMD-K6-2E | |
| Descripción | Embedded Processor | |
| Fabricantes | AMD | |
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Preliminary Information
®
AMD-K6TM-2E
Embedded Processor
www.DataSheet4U.com
Data Sheet
Publication # 22529 Rev: B
Issue Date: Jan 2000
Amendment/0
1 page  
22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Contents
Revision History.......................................................................... xv
About this Data Sheet...............................................................xvii
Overview ................................................................................. xvii
1 AMD-K6™-2E Processor .............................................................. 1
1.1 AMD-K6™-2E Embedded Processor Features ......................... 2
1.2 Process Technology..................................................................... 4
1.3 Super7™ Platform Initiative ..................................................... 4
2 Internal Architecture .................................................................. 7
2.1 AMD-K6™-2E Processor Microarchitecture Overview ........... 7
2.2 Cache, Instruction Prefetch, and Predecode Bits.................. 12
2.3 Instruction Fetch and Decode ................................................. 13
2.4 Centralized Scheduler .............................................................. 17
2.5 Execution Units......................................................................... 18
2.6 Branch-Prediction Logic........................................................... 20
3 Software Environment ............................................................... 23
3.1 Registers .................................................................................... 23
3.2 Model-Specific Registers (MSR) ............................................. 40
3.3 Memory Management Registers.............................................. 47
3.4 Paging......................................................................................... 49
3.5 Descriptors and Gates .............................................................. 52
3.6 Exceptions and Interrupts ....................................................... 55
3.7 Instructions Supported by the AMD-K6™-2E Processor ...... 56
4 Logic Symbol Diagram ............................................................... 83
5 Signal Descriptions .................................................................... 85
5.1 Signal Terminology................................................................... 85
5.2 A20M# (Address Bit 20 Mask) ................................................. 86
5.3 A[31:3] (Address Bus)............................................................... 87
5.4 ADS# (Address Strobe) ............................................................ 88
5.5 ADSC# (Address Strobe Copy) ................................................ 88
5.6 AHOLD (Address Hold) ........................................................... 89
5.7 AP (Address Parity).................................................................. 90
5.8 APCHK# (Address Parity Check)............................................ 91
5.9 BE[7:0]# (Byte Enables) ........................................................... 92
5.10 BF[2:0] (Bus Frequency) .......................................................... 93
5.11 BOFF# (Backoff) ....................................................................... 94
5.12 BRDY# (Burst Ready)............................................................... 95
5.13 BRDYC# (Burst Ready Copy) .................................................. 96
5.14 BREQ (Bus Request)................................................................. 96
5.15 CACHE# (Cacheable Access) .................................................. 97
5.16 CLK (Clock) ............................................................................... 97
5.17 D/C# (Data/Code) ...................................................................... 98
5.18 D[63:0] (Data Bus)..................................................................... 99
5.19 DP[7:0] (Data Parity).............................................................. 100
5.20 EADS# (External Address Strobe)........................................ 101
Contents
v
5 Page 
22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
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Debug Registers DR5 and DR4....................................242
Debug Registers DR3, DR2, DR1, and DR0................243
Clock Control State Transitions...................................248
Suggested Component Placement ...............................263
CLK Waveform ..............................................................269
Key to Timing Diagrams ...............................................281
Output Valid Delay Timing ..........................................281
Maximum Float Delay Timing .....................................282
Input Setup and Hold Timing ......................................282
Reset and Configuration Timing .................................283
TCK Timing....................................................................284
TRST# Timing................................................................284
Test Signal Timing ........................................................284
Thermal Model ..............................................................286
Power Consumption v. Thermal Resistance ...............287
Processor Heat Dissipation Path .................................288
Measuring Case Temperature......................................289
Heatsink A (15 mm height) ..........................................290
Heatsink B (20 mm height)...........................................290
Heatsink C (30 mm height) ..........................................290
Measured Thermal Resistance v. Airflow
(Socketed 321-Pin CPGA Package) .............................291
Measured Maximum Ambient Temperature
(Socketed 321-Pin CPGA Package) .............................292
Measured Thermal Resistance v. Airflow
(Soldered 321-Pin CPGA Package)..............................293
Measured Maximum Ambient Temperature
(Soldered, 321-Pin CPGA Package).............................294
Voltage Regulator Placement ......................................295
Airflow for a Heatsink with Fan ..................................296
Airflow Path in a Dual-Fan System .............................296
Airflow Path in an ATX Form-Factor System ............297
AMD-K6™-2E Processor Connection Diagram
(Top-Side View CPGA) .................................................299
AMD-K6™-2E Processor Connection Diagram
(Bottom-Side View CPGA)............................................300
321-Pin Staggered CPGA Package Specification .......303
List of Figures
xi
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