PDF AT91CAP9S500A Data sheet ( Hoja de datos )

Número de pieza	AT91CAP9S500A
Descripción	(AT91CAP9S250A / AT91CAP9S500A) Customizable Microcontroller Processor
Fabricantes	ATMEL Corporation
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Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support • Additional Embedded Memories – One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed • External Bus Interface (EBI) – EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory, Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash™ • Metal Programmable (MP) Block – 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers) for AT91CAP9S500A/AT91CAP9S250A Respectively – Ten 512 x 36-bit Dual Port RAMs – Eight 512 x 72-bit Single Port RAMs – High Connectivity for Up to Three AHB Masters and Four AHB Slaves – Up to Seven AIC Interrupt Inputs – Up to Four DMA Hardware Handshake Interfaces – Delay Lines for Double Data Rate Interface – UTMI+ Full Connection – Up to 77 Dedicated I/Os • LCD Controller www.DataSheet4U.com – Supports Passive or Active Displays – Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider Screen Buffers • Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format • USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port – Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels • USB 2.0 High Speed (480 Mbits per second) Device Port – On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM – Integrated FIFOs and Dedicated DMA Channels – Integrated UTMI+ Physical Interface • Ethernet MAC 10/100 Base T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit • Multi-Layer Bus Matrix – Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus Bandwidth at Maximum 100 MHz System Clock Speed – Boot Mode Select Option, Remap Command • Fully-featured System Controller, Including – Reset Controller, Shutdown Controller Customizable Microcontroller Processor AT91CAP9S500A AT91CAP9S250A Summary Preliminary 6264AS–CAP–21-May-07 1 page AT91CAP9S500A/AT91CAP9S250A 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Description List Signal Name VDDIOM VDDIOP0 VDDIOP1 VDDIOMPA VDDIOMPB VDDBU VDDPLL VDDUTMII VDDUTMIC VDDUPLL VDDANA VDDCORE GND GNDPLL GNDUTMII GNDUTMIC GNDUPLL GNDANA GNDBU GNDTHERMAL XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 SHDN WKUP Function Power Supplies EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply MP Block I/O A Lines Power Supply MP Block I/O B Lines Power Supply Backup I/O Lines Power Supply PLL Power Supply USB UTMI+ Interface Power Supply USB UTMI+ Core Power Supply USB UTMI+ PLL Power Supply ADC Analog Power Supply Core Chip Power Supply Ground PLL Ground USB UTMI+ Interface Ground USB UTMI+ Core Ground USB UTMI+ PLL Ground ADC Analog Ground Backup Ground Type Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Thermal Ground Ball Ground Clocks, Oscillators and PLLs Main Oscillator Input Input Main Oscillator Output Output Slow Clock Oscillator Input Input Slow Clock Oscillator Output Output PLL A Filter Input PLL B Filter Input Programmable Clock Output Output Shutdown, Wakeup Logic Shutdown Control Output Wake-Up Input Input Active Level Comments 1.65V to 3.6V 3.0V to 3.6V 1.65V to 3.6V 1.65V to 3.6V 1.65V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 3.0V to 3.6V 1.08V to 1.32V Thermally coupled with package substrate Do not tie over VDDBU Accept between 0V and VDDBU 6264AS–CAP–21-May-07 5 5 Page AT91CAP9S500A/AT91CAP9S250A 4.2 400-ball BGA Package Pinout Table 4-1. AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package Pin Signal Name Pin Signal Name Pin Signal Name A1 PC5 F1 PA3 L1 PA22 A2 PC3 F2 PA4 L2 PA25 A3 PC2 F3 PA8 L3 PA29 A4 PC1 F4 PA5 L4 PA31 A5 PC0 F5 PA6 L5 PD6 A6 BMS F6 VDDIOM L6 GNDIO A7 NRST F7 VDDIOP0 L7 GNDCORE A8 GNDCORE F8 PC24 L8 PA18 A9 PB18 F9 NC L9 GNDTHERMAL A10 PB17 F10 VDDCORE L10 GNDTHERMAL A11 PB14 F11 GNDIO L11 GNDTHERMAL A12 PB15 F12 PB23 L12 GNDTHERMAL A13 GNDANA F13 PB6 L13 GNDCORE A14 PB26 F14 NC L14 GNDIO A15 VDDIOP0 F15 NC L15 VDDCORE A16 GNDIO F16 NC L16 MPIOB28 A17 FSDP F17 GNDPLL L17 MPIOB32 A18 FSDM F18 WKUP0 L18 MPIOB34 A19 HSDP F19 SHDW L19 MPIOB31 A20 HSDM F20 PLLRCA L20 MPIOB29 B1 PC17 G1 PA7 M1 PA26 B2 PC16 G2 PA10 M2 PA30 B3 PC14 G3 PA11 M3 PD11 B4 PC11 G4 PA9 M4 PD12 B5 PC10 G5 PA12 M5 PD13 B6 PC9 G6 PD10 M6 PD15 B7 TDO G7 GNDIO M7 GNDCORE B8 TCK G8 GNDCORE M8 PA28 B9 PB20 G9 VDDIOP0 M9 GNDTHERMAL B10 PB19 G10 PC8 M10 GNDTHERMAL B11 PB13 G11 PB25 M11 GNDTHERMAL B12 ADVREF G12 PB21 M12 GNDTHERMAL B13 PB16 G13 PB8 M13 NRD B14 PB27 G14 PB0 M14 MPIOB26 B15 PB24 G15 PB2 M15 GNDIO B16 HDMA G16 NC M16 MPIOB16 B17 VDDIOP0 G17 VDDPLL M17 GNDCORE 6264AS–CAP–21-May-07 Pin Signal Name T1 PD22 T2 PD23 T3 PD30 T4 VDDCORE T5 SDDRCS T6 DQS0 T7 D4 T8 D11 T9 D14 T10 SDA10 T11 VDDCORE T12 MPIOA0 T13 MPIOA9 T14 GNDIO T15 MPIOA25 T16 MPIOA24 T17 MPIOA29 T18 MPIOB3 T19 MPIOB17 T20 MPIOB18 U1 PD25 U2 PD31 U3 BCCLK U4 A0 U5 D0 U6 D1 U7 NWR1 U8 DQS1 U9 A7 U10 A13 U11 A20 U12 GNDIO U13 MPIOA4 U14 MPIOA11 U15 MPIOA16 U16 VDDMPIOA U17 MPIOA23 11 11 Page

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