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PDF MSC8101 Data sheet ( Hoja de datos )
| Número de pieza | MSC8101 | |
| Descripción | Network Digital Signal Processor | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MSC8101 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Freescale Semiconductor
Technical Data
MSC8101
Rev. 16, 11/2004
MSC8101
Network Digital Signal Processor
CPM
UTOPIA
Interface
MII
3 × FCC
2 × MCC
4 × SCC
Interrupt
Controller
Timers
Parallel I/O
Baud Rate
Generators
{•
TDMs •
•
2 × SMC
SPI
Dual Ported
RAM
2 × SDMA
Other
Peripherals
I2C
Extended Core
Program
Sequencer
Address
Register
File
RISC
Data ALU
Register
File
www.DataSheet4U.com
SC140
Core
Address
ALU
Data
ALU
JTAG
EOnCE™
Power
Management
Clock/PLL
SIU
64-bit System Bus
MEMC
DMA
Engine
PIT
System Protection
Reset Control
Clock Control
64/32-bit
System
Bus
Bridge
SIC_EXT
SIC
Interrupts
The Freescale MSC8101
16-bit DSP is the first
member of the family of
DSPs based on the
StarCore SC140 DSP core.
The MSC8101 is available
in three core speed levels:
250, 275, and 300 MHz.
MEMC
64-bit Local Bus
Q2PPC 128-bit QBus
Bridge
PIC
EFCOP
Boot
ROM
HDI16
SRAM
512 KB
L1 Interface
Interrupts
8/16-bit
Host
Interface
128-bit P-Bus
64-bit XA Data Bus
64-bit XB Data Bus
What’s New?
Rev. 16 includes the following
changes:
• Changed most REFCLK
references to DLLIN in
Section 2.7.4.
Figure 1. MSC8101 Block Diagram
The Freescale MSC8101 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (arithmetic
logic unit) DSP core along with 512 KB of internal memory, a communications processor module (CPM), a 64-bit bus, a very
flexible System Integration Unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the
MSC8101 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM is a 32-
bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet,
and asynchronous transfer mode (ATM) backbones. The MSC8101 60x-compatible bus interface facilitates its connection to
multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data
memories. The MSC8101 offers 1500 DSP MMACS (1200 core and 300 EFCOP) performance using an internal 300 MHz
clock with a 1.6 V core and independent 3.3 V input/output (I/O).
© Freescale Semiconductor, Inc., 2001, 2004. All rights reserved.
1 page  
Signals/Connections
1
The MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and
Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and
references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8101
external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are
multiplexed. Because the parallel I/O design supported by the MSC8101 communications processor module
(CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered
sequentially.
Table 1-1. MSC8101 Functional Signal Groupings
Functional Group
Number of Signal
Connections
Detailed Description
Power (VCC, VDD, and GND)
Clock
Reset, configuration, and EOnCE
System bus, HDI16, and interrupts
Memory Controller
CPM Input/Output Parallel Ports
JTAG Test Access Port
Reserved (denotes connections that are always reserved)
Port A
Port B
Port C
Port D
80 Table 1-2 on page 1-4
6 Table 1-3 on page 1-4
11 Table 1-4 on page 1-5
133 Table 1-5 on page 1-7
27 Table 1-6 on page 1-13
26 Table 1-7 on page 1-16
14 Table 1-8 on page 1-21
18 Table 1-9 on page 1-24
8 Table 1-10 on page 1-33
5 Table 1-11 on page 1-36
5 Table 1-12 on page 1-36
Freescale Semiconductor
MSC8101 Technical Data, Rev. 16
1-1
5 Page 
System Bus, HDI16, and Interrupt Signals
Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external lines
that can connect to these internal signal lines. After reset, the default configuration includes two IRQ1 and two IRQ7
input lines. The designer must select one line for each required interrupt and reconfigure the other external signal
line or lines for alternate functions.
Table 1-5. System Bus, HDI16, and Interrupt Signals
Signal
A[0–31]
TT[0–4]
TSIZ[0–3]
TBST
IRQ1
GBL
Reserved
BADDR29
IRQ2
Reserved
BADDR30
IRQ3
Reserved
BADDR31
IRQ5
Data Flow
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input/Output
Output
Output
Input
Output
Output
Input
Output
Output
Input
Description
Address Bus
When the MSC8101 is in external master bus mode, these pins function as the address bus. The
MSC8101 drives the address of its internal bus masters and responds to addresses generated by
external bus masters. When the MSC8101 is in Internal Master Bus mode, these pins are used as
address lines connected to memory devices and are controlled by the MSC8101 memory controller.
Bus Transfer Type
The bus master drives these pins during the address tenure to specify the type of transaction.
Transfer Size
The bus master drives these pins with a value indicating the number of bytes transferred in the
current transaction.
Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst transaction
(transfers four quad words).
Interrupt Request 11
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Global1
When a master within the chip initiates a bus transaction, it drives this pin. When an external master
initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is
global and it should be snooped by caches in the system.
The primary configuration is reserved.
Burst Address 291
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8101 memory controller.
Interrupt Request 21
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
The primary configuration is reserved.
Burst Address 301
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8101 memory controller.
Interrupt Request 31
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
The primary configuration is reserved.
Burst Address 311
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8101 memory controller.
Interrupt Request 51
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Freescale Semiconductor
MSC8101 Technical Data, Rev. 16
1-7
11 Page | ||
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| PDF Descargar | [ Datasheet MSC8101.PDF ] | |
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