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PDF ADP3192A Data sheet ( Hoja de datos )
| Número de pieza | ADP3192A | |
| Descripción | 8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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8-Bit Programmable 2- to 4-Phase
Synchronous Buck Controller
ADP3192A
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
±7.7 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Fast enhanced PWM (FEPWM) flex mode for excellent load
transient performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output supports both
VR10.x and VR11 specifications
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for next generation
Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP3192A1 is a highly efficient, multiphase, synchronous
buck-switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 8-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.5 V and 1.6 V.
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
or 4-phase operation, allowing for the construction of up to
four complementary buck-switching stages.
FUNCTIONAL BLOCK DIAGRAM
VCC
31
RT RAMPADJ
12 13
GND 18
SHUNT
REGULATOR
UVLO
SHUTDOWN
850mV –
EN 1
+
DAC
+ 150mV
CSREF
–
+
+
DAC –
– 350mV
PWRGD 2
DELAY
OSCILLATOR
19 OD
+
CMP
–
+
CMP
–
+
CMP
–
+
CMP
–
SET EN
RESET
30 PWM1
RESET
29 PWM2
RESET
28 PWM3
2/3/4-PHASE
DRIVER LOGIC 27 PWM4
RESET
CROWBAR
CURRENT
LIMIT
TTSENSE 10
VRHOT 9
VRFAN 8
THERMAL
THROTTLING
CONTROL
25 SW1
24 SW2
23 SW3
22 SW4
ILIMIT 11
DELAY 7
17 CSCOMP
CURRENT
MEASUREMENT
+
15 CSREF
AND LIMIT
– 16 CSSUM
21 IMON
IREF 20
COMP 5
4 FB
FBRTN 3
PRECISION
REFERENCE
VIDSEL 40
VID DAC
32 33 34 35 36 37 38 39
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
BOOT
VOLTAGE
AND
SOFT START
CONTROL
14 LLSET
6 SS
ADP3192A
Figure 1.
The ADP3192A also includes programmable no load offset and
slope functions to adjust the output voltage as a function of the
load current, optimally positioning it for a system transient. In
addition, the ADP3192A provides accurate and reliable short-
circuit protection, adjustable current limiting, and a delayed
power-good output that accommodates on-the-fly output
voltage changes requested by the CPU.
The ADP3192A has a built-in shunt regulator that allows the part
to be connected to the 12 V system supply through a series resistor.
The ADP3192A is specified over the extended commercial
temperature range of 0°C to 85°C and is available in a
40-lead LFCSP.
1 Protected by U.S. Patent Number 6,683,441; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
TEST CIRCUITS
12V
8-BIT CODE
40
1.25V
1kΩ
10nF
10nF
1
EN
PWRGD
FBRTN
FB
COMP
SS
DELAY
VRFAN
VRHOT
TTSENSE
ADP3192A
680Ω
680Ω
+ 1µF
100nF
PWM1
PWM2
PWM3
PWM4
NC
SW1
SW2
SW3
SW4
NC
100kΩ
NC = NO CONNECT
250kΩ
20kΩ
100nF
Figure 2. Closed-Loop Output Voltage Accuracy
12V
680Ω
39kΩ
1kΩ
1V
ADP3192A
680Ω
VCC
31
CSCOMP
17
100nF
CSSUM
16
CSREF
15
GND
18
VOS =
CSCOMP – 1V
40
Figure 3. Current Sense Amplifier VOS
ADP3192A
12V ADP3192A
680Ω
10kΩ
680Ω
VCC
31
COMP
5
FB
4
LLSET –
14
ΔV
CSREF
15 +
1V
GND
18
VID
DAC
ΔVFB = FBΔV = 80mV – FBΔV = 0mV
Figure 4. Positioning Voltage
Rev. 0 | Page 5 of 32
5 Page 
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3192A is set with an external
resistor connected from the RT pin to GND. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If all
phases are in use, divide by 4. If PWM4 is tied to VCC, divide
the master clock by 3 for the frequency of the remaining phases.
If PWM3 and PWM4 are tied to VCC, divide by 2.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3192A combines differential sensing with a high
accuracy VID DAC and reference, and a low offset error ampli-
fier. This maintains a worst-case specification of ±7.7 mV
differential sensing error over its full operating output voltage
and temperature range. The output voltage is sensed between
the FB pin and FBRTN pin. FB should be connected through
a resistor to the regulation point, usually the remote sense pin
of the microprocessor. FBRTN should be connected directly
to the remote sense ground point. The internal VID DAC
and precision reference are referenced to FBRTN, which has a
minimal current of 65 μA to allow accurate remote sensing. The
internal error amplifier compares the output of the DAC to the
FB pin to regulate the output voltage.
OUTPUT CURRENT SENSING
The ADP3192A provides a dedicated current-sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load. This is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways, depending on
the objectives of the system, as follows:
• Output inductor DCR sensing without a thermistor for
lowest cost
• Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature
• Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the sensing
element, such as the switch node side of the output inductors,
to the inverting input CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier and a filter
capacitor is placed in parallel with this resistor. The gain of the
amplifier is programmable by adjusting the feedback resistor.
ADP3192A
An additional resistor divider connected between CSREF and
CSCOMP (with the midpoint connected to LLSET) can be used
to set the load line required by the microprocessor. The current
information is then given as CSREF − LLSET. This difference
signal is used internally to offset the VID DAC for voltage
positioning. The difference between CSREF and CSCOMP is
then used as a differential input for the current-limit comparator.
This allows the load line to be set independently of the current-
limit threshold. In the event that the current-limit threshold
and load line are not independent, the resistor divider between
CSREF and CSCOMP can be removed, and the CSCOMP pin
can be directly connected to LLSET. To disable voltage position-
ing entirely (that is, no load line), connect LLSET to CSREF.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing gain
is determined by external resistors to make it extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the LLSET pin can be scaled to equal the regulator droop
impedance multiplied by the output current. This droop voltage
is then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input
voltage to tell the error amplifier where the output voltage
should be. This allows enhanced feed-forward response.
CURRENT CONTROL MODE AND THERMAL
BALANCE
The ADP3192A has individual inputs (SW1 to SW4) for each
phase that are used for monitoring the current of each phase.
This information is combined with an internal ramp to create
a current balancing feedback system that has been optimized for
initial current balance accuracy and dynamic thermal balancing
during operation. This current balance information is independent
of the average output current information used for positioning
as described in the Output Current Sensing section.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. External
resistors can be placed in series with individual phases to create
an intentional current imbalance if desired, such as when one
phase has better cooling and can support higher currents.
Resistor RSW1 through Resistor RSW4 (see Figure 10) can be used
for adjusting thermal balance in this 4-phase example. It is best
to have the ability to add these resistors during the initial design;
therefore, ensure that placeholders are provided in the layout.
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3192A.PDF ] | |
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