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PDF T431616B Data sheet ( Hoja de datos )

Número de pieza T431616B
Descripción 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
Fabricantes TMT 
Logotipo TMT Logotipo



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No Preview Available ! T431616B Hoja de datos, Descripción, Manual

tm TE
CH
SDRAM
T431616B
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
FEATURES
+2.7 to +3.6V power supply
Dual banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going edge
of system clock
Burst Read Single-bit Write operation
DQM for masking
Auto refresh and self refresh
32ms refresh period (2K cycle)
MRS cycle with address key programs
- CAS Latency ( 1 & 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
Available package type in 50 pin TSOP(II)
and 60-pin CSP
ORDERING INFORMATION
MAX
PART NO. FREQUENCY PACKAGE
T431616B-20S
T431616B-20C
T431616B-10S
T431616B-10C
50 MHz
50 MHz
100 MHz
100 MHz
TSOP-II
CSP
TSOP-II
CSP
GRNERAL DESCRIPTION
The T431616B is 16,777,216 bits synchronous
high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clockcycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: JUL. 2001
Revision:A

1 page




T431616B pdf
tm TE
CH
T431616B
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on Any Pin Relative To Vss
V I N,VOUT
-1.0 to 4.6
Supply Voltage Relative To Vss
V D D,VDDQ
-1.0 to 4.6
Short circuit Output Current
Power Dissipation
Iout 50
PD 1
Operating Temperature
TOPR
-10 to +85
Storage Temperature
Tstg -55 to 125
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
mA
W
°C
°C
RECOMMENDED DC OPERATING CONDITIONS
(TA = -10 to +85° C , Voltage referenced to VS S=0V)
Parameter
Symbol
Min.
Typ
Max.
Supply Voltage
V D D,VDDQ
2.7
3.3
3.6
Input High Voltage VIH 2.0 3.0 VDD+0.3V
Input Low Voltage
VIL -0.3
0
0.8
Output logic high voltage
VOH
2.4
-
-
Output logic low voltage
VO L
-
-
0.4
Input leakage current
IIL
-5
-
5
Output leakage current
IOL
-5
-
5
Note : 1. VIH (max) = 4.6V AC for pulse width 10ns acceptable.
2. VIL (min) = -1.0V AC for pulse width 10ns acceptable.
3. Any input 0V VIN VDD+ 0.3V , all other pin are not under test = 0V.
4. Dout = disable , 0V VOUT VDD .
Unit Notes
V
V1
V2
V IOH=-2mA
V IOL=2mA
uA 3
uA 4
CAPACITANCE
(TA =25°C ,VDD=3.3V, f = 1MHz)
Pin
Symbol
Min
Max
Unit
CLOCK
CCLK 2.5 4.0 pF
ADDRESS
CADD 2.5 5.0 pF
DQ0 ~ DQ15
COUT 4.0 6.5 pF
RAS,CAS,WE,CS,CKE,LDQM,
CIN
2.5 5.0 pF
UDQM
Taiwan Memory Technology, Inc. reserves the right P. 5
to change products or specifications without notice.
Publication Date: JUL. 2001
Revision:A

5 Page





T431616B arduino
tm TE
CH
T431616B
MODE REGISTER
11 10 9 8 7 6 5 4 3 2 1 0
00001
JEDEC Standard Test Set (refresh counter test)
11 10 9 8 7 6 5 4
3 210
x x 1 0 0 LTMODE WT BL Burst Read and Single Write (for Write Through Cache)
11 10
98 7654
10
3 210
Use in future
11 10 9 8 7 6 5 4 3 2 1 0
x x x 1 1 v v v v v v v Vender Specific
11 10 9 8 7 6 5
0 0 0 0 0 LTMODE
4 3 21 0
WT BL Mode Register Set
v = Valid
x = Don’t care
Burst length
Bit2-0
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
Full page
WT=1
1
2
4
8
R
R
R
R
Wrap type
0
1
Sequential
Interleave
Mode Register Write Timing
Latency mode
Bit6-4
000
001
010
011
100
101
110
111
CAS Latency
R
R
2
3
R
R
R
R
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Taiwan Memory Technology, Inc. reserves the right P.11
to change products or specifications without notice.
Publication Date: JUL. 2001
Revision:A

11 Page







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