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PDF T431616E Data sheet ( Hoja de datos )
| Número de pieza | T431616E | |
| Descripción | (T431616D/E) 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM | |
| Fabricantes | TMT | |
| Logotipo |  |
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tm TE
CH
SDRAM
T431616D/E
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
FEATURES
Fast access time: 5/6/7 ns
• Fast clock rate: 200/166/143 MHz
• Self refresh mode: standard and low power
• Internal pipelined architecture
• 512K word x 16-bit x 2-bank
• Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
• Individual byte controlled by LDQM and UDQM
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• JEDEC standard +3.3V±0.3V power supply
• Interface: LVTTL
• 50-pin 400 mil plastic TSOP II package
• 60-ball, 6.4x10.1mm VFBGA package
• Lead Free Package available for both TSOP II and
VFBGA
•Low Operating Current for T431616E
Key Specifications
tCK3
tRAS
tAC3
tRC
T431616D/E
Clock Cycle time(min.)
Row Active time(max.)
Access time from CLK(max.)
Row Cycle time(min.)
-5/6/7
5/6/7ns
35/42/42 ns
4.5/5/5.5 ns
48/54/63 ns
ORDERING INFORMATION
GRNERAL DESCRIPTION
The T431616D/E SDRAM is a high-speed CMOS
synchronous DRAM containing 16 Mbits. It is internally
configured as a dual 512K word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 16 bit banks is organized as 2048 rows by 256
columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The T431616D/E provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to
use. By having a programmable mode register, the
system can choose the most suitable modes to maximize
its performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications
Part Number
T431616D-5S/C
T431616D-5SG/CG
T431616D-6S/C
T431616D-6SG/CG
T431616D-7S/C
T431616D-7SG/CG
T431616E-7S/C
T431616E-7SG/CG
G : indicates Lead Free Package
Frequency
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
143MHz
143MHz
Package
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
1 page  
tm TE
CH
T431616D/E
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the
truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#
BankActivate
Idle(3)
HX
X VV V L L
HH
BankPrecharge
Any H X X V L X L L H L
PrechargeAll
Any H X X X H X L L H L
Write
Active(3) H
X
X VL V L H
LL
Write and AutoPrecharge
Active(3) H
X
X VH V L H
LL
Read
Active(3) H
X
X VL V L H
LH
Read and Autoprecharge
Active(3) H
X
X VH V L H
LH
Mode Register Set
Idle
HX
X VV V L L
LL
No-Operation
Any H X X X X X L H H H
Burst Stop
Active(4) H
X
X XX X L H H L
Device Deselect
Any H X X X X X H X X X
AutoRefresh
Idle
HH
X XX X L L
LH
SelfRefresh Entry
Idle H L X X X X L L L H
SelfRefresh Exit
Idle
LH
X XX X H X X X
(SelfRefresh)
LH HH
Clock Suspend Mode Entry
Active H L
X XX X X X X X
Power Down Mode Entry
Any(5) H L
X XX X H X X X
LH HH
Clock Suspend Mode Exit
Active L H X X X X X X X X
Power Down Mode Exit
Any L H X X X X H X X X
(PowerDown)
LH HH
Data Write/Output Enable
Active H X
L XX X X X X X
Data Mask/Output Disable
Active H X
H XX X X X X X
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
5 Page 
tm TE
CH
T431616D/E
6 Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the write
operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst
length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the
auto precharge function is ignored.
T0 T1
T2 T3
T4 T5
T6 T7
T8
CLK
COMMAND
Bank A
Activate
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
NOP
NOP
Write A
AutoPrecharge
NOP
NOP
NOP
DIN A0
DIN A1
tDAL
*
DIN A0
DIN A1
tDAL
*
DIN A0
DIN A1
*
tDAL
NOP
NOP
tDAL= tWR + tRP
* Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 1, 2, 3)
7 Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode
register to make SDRAM useful for a variety of different applications. The default values of the Mode Register
after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins
A0~A9 and A11 in the same cycle is the data written to the mode register. One clock cycle is required to
complete the write in the mode register (refer to the following figure). The contents of the mode register can be
changed using the same command and the clock cycle requirements during operation as long as both banks are in
the idle state.
TM Technology Inc. reserves the right
P. 11
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet T431616E.PDF ] | |
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