Datasheet.kr   

K7I643682M 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K7I643682M은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 K7I643682M 자료 제공

부품번호 K7I643682M 기능
기능 (K7I643682M / K7I641882M) 72Mb M-die DDRII SRAM Specification 165 FBGA
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


K7I643682M 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 17 페이지수

미리보기를 사용할 수 없습니다

K7I643682M 데이터시트, 핀배열, 회로
K7I643682M
K7I641882M
2Mx36 & 4Mx18 DDRII CIO b2 SRAM
72Mb M-die DDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
www.DataSheet4U.com
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Aug. 2005
Rev 1.0




K7I643682M pdf, 반도체, 판매, 대치품
K7I643682M
K7I641882M
2Mx36 & 4Mx18 DDRII CIO b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I643682M(2Mx36)
1 2 3 4 5 6 7 8 9 10 11
A
CQ VSS/SA* SA
R/W
BW2
K
BW1
LD
SA
SA
CQ
B NC DQ27 DQ18 SA BW3
K
BW0
SA
NC
NC DQ8
C NC
NC DQ28 VSS
SA
SA0
SA
VSS
NC
DQ17
DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ2
M NC
NC DQ34 VSS VSS VSS VSS VSS
NC
DQ11
DQ1
N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10
P NC
NC DQ26 SA
SA
C
SA
SA
NC
DQ9
DQ0
R TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb .
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
NOTE
K, K 6B, 6A
Input Clock
C, C
6P, 6R
Input Clock for Output Data
1
CQ, CQ
11A, 1A
Output Echo Clock
Doff 1H
DLL Disable when low
SA0 6C Burst Count Address Inputs
SA 3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
DQ0-35
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
Data Inputs Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW3
7B,7A,5A,5B
Block Write Control Pin,active when low
VREF
2H,10H
Input Reference Voltage
ZQ 11H Output Driver Impedance Control Input 2
VDD
VDDQ
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
VSS
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
Ground
TMS 10R JTAG Test Mode Select
TDI 11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
NC 1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 4 - Aug. 2005
Rev 1.0

4페이지










K7I643682M 전자부품, 판매, 대치품
K7I643682M
K7I641882M
2Mx36 & 4Mx18 DDRII CIO b2 SRAM
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250resistor will give an output impedance of 50.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous
behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.
Clock Consideration
K7I643682M and K7I641882M utlizes internal DLL(Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
- 7 - Aug. 2005
Rev 1.0

7페이지


구       성 총 17 페이지수
다운로드[ K7I643682M.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
K7I643682M

(K7I643682M / K7I641882M) 72Mb M-die DDRII SRAM Specification 165 FBGA

Samsung semiconductor
Samsung semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵