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PDF K7I641884M Data sheet ( Hoja de datos )
| Número de pieza | K7I641884M | |
| Descripción | (K7I641884M / K7I643684M) 72Mb DDRII SRAM Specification | |
| Fabricantes | Samsung semiconductor | |
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K7I643684M
K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
72Mb DDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
www.DataSheet4U.com
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Rev. 1.3 March 2007
1 page  
K7I643684M
K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I641884M(2Mx18)
123456
A CQ
SA
SA
R/W
BW1
K
B NC DQ9 NC SA NC
K
C NC NC NC VSS SA SA0
D NC
NC DQ10 VSS VSS VSS
E NC
NC
DQ11
VDDQ
VSS
VSS
F NC DQ12 NC VDDQ VDD VSS
G NC
NC
DQ13
VDDQ
VDD
VSS
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
J
NC
NC
NC VDDQ VDD
VSS
K NC
NC
DQ14
VDDQ
VDD
VSS
L NC DQ15 NC VDDQ VSS VSS
M NC
NC
NC
VSS
VSS
VSS
N NC NC DQ16 VSS SA SA
P NC
NC DQ17 SA
SA
C
R TDO TCK
SA
SA
SA
C
Notes: 2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
7
NC
BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
LD
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA0,SA1
SA
DQ0-17
R/W
LD
BW0, BW1
VREF
ZQ
VDD
VDDQ
VSS
TMS
TDI
TCK
TDO
NC
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
6C,7C
2A,3A,9A,10A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
NOTE
1
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply (1.8 V)
Output Power Supply (1.5V or 1.8V)
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
2
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 5 - Rev. 1.3 March 2007
5 Page 
K7I643684M
K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.2
-
MAX
-
VREF - 0.2
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transition edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
UNIT
V
V
NOTES
1,2
1,2
PARAMETER
SYMBOL
Clock
Clock Cycle Time (K, K, C, C)
tKHKH
Clock Phase Jitter (K, K, C, C)
tKC var
Clock High Time (K, K, C, C)
tKHKL
Clock Low Time (K, K, C, C)
tKLKH
Clock to Clock (K↑ → K↑, C↑ → C↑)
tKHKH
Clock to data clock (K↑ → C↑, K↑→ C↑)
tKHCH
DLL Lock Time (K, C)
tKC lock
K Static to DLL reset
tKC reset
Output Times
C, C High to Output Valid
tCHQV
C, C High to Output Hold
tCHQX
C, C High to Echo Clock Valid
tCHCQV
C, C High to Echo Clock Hold
tCHCQX
CQ, CQ High to Output Valid
tCQHQV
CQ, CQ High to Output Hold
tCQHQX
C, High to Output High-Z
tCHQZ
C, High to Output Low-Z
tCHQX1
Setup Times
Address valid to K rising edge
tAVKH
Control inputs valid to K rising edge tIVKH
Data-in valid to K, K rising edge
tDVKH
Hold Times
K rising edge to address hold
tKHAX
K rising edge to control inputs hold tKHIX
K, K rising edge to data-in hold
tKHDX
-30
MIN MAX
3.30
1.32
1.32
1.49
0.00
1024
30
8.40
0.20
1.45
-0.45
-0.45
-0.27
-0.45
0.45
0.45
0.27
0.45
0.40
0.40
0.30
0.40
0.40
0.30
-25
MIN MAX
4.00
1.60
1.60
1.80
0.00
1024
30
8.40
0.20
1.80
-0.45
-0.45
-0.30
-0.45
0.45
0.45
0.30
0.45
0.50
0.50
0.35
0.50
0.50
0.35
-20
MIN MAX
5.00
2.00
2.00
2.20
0.00
1024
30
8.40
0.20
2.30
-0.45
-0.45
-0.35
-0.45
0.45
0.45
0.35
0.45
0.60
0.60
0.40
0.60
0.60
0.40
-16
UNIT NOTE
MIN MAX
6.00
2.40
2.40
2.70
0.00
1024
30
8.40
0.20
2.80
ns
ns
ns
ns
ns
ns
cycle
ns
5
6
-0.50
-0.50
-0.40
-0.50
0.50
0.50
0.40
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
7
7
3
3
0.70 ns
0.70 ns 2
0.50 ns
0.70 ns
0.70 ns
0.50 ns
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and BW2, BW3, also for x36
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1 ns variation from echo clock to data.
The data sheet parameters reflect tester guard bands and test setup variations.
- 11 - Rev. 1.3 March 2007
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet K7I641884M.PDF ] | |
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