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PDF MSX532 Data sheet ( Hoja de datos )
| Número de pieza | MSX532 | |
| Descripción | 532 Port Digital Crosspoint Switch | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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June 2002
Revised April 2003
MSX532
532 Port Digital Crosspoint Switch with LVTTL I/O’s
General Description
The MSX family of SRAM-based bit-oriented switching
devices offer flow-through NRZ data rates of up to 150Mb/s
and registered clock frequencies of up to 75MHz. The I/O
buffers are individually configurable. The I/O buffers can be
connected to each other through the switch matrix, which
supports One-to-One and One-to-Many connections.
The proprietary RapidConfigure parallel interface allows
fast configuration of both the I/O buffers and switch matrix.
It also allows readback of the device for test and verifica-
tion purposes. The MSX devices also support the industry
standard JTAG (IEEE 1149.1) interface for boundary scan
testing. The JTAG interface can also be used to download
configuration data to the device. A functional block diagram
of the MSX architecture is shown in Figure 1.
Features
s SRAM-based, in-system programmable
s Configurable I/O Ports
• Individually programmable as input, output,
bi-directional, or Bus Repeater mode
• Control Signals per I/O port: 2 input enables, 2 output
enables, 2 Global Clock inputs and Next Neighbor
Clock option
• Output data inversion: capable of inverting output
signals in flow through mode
s Non-blocking switch matrix
• One-to-One and One-to-Many connections
Double-buffered configuration RAM cells
simultaneous global updates
s Registered and flow-through data modes
for
• Up to 75 MHz clock frequency in registered mode
• Up to 150 Mb/s in flow-through mode
s 20 ns propagation delay in flow-through mode
s 8 mA output current
s Dedicated RapidConfigure parallel interface or JTAG
serial interface available for configuration and readback
of MSX devices
s 3.3V operation, LVTTL I/O's (5V tolerant)
s MSX532 is offered in a 792 TBGA package
Applications
• Telecom and datacom switching
• Video switches and servers
• Test equipment
Ordering Code:
Order Number
MSX532TB792
Package Number
Package Description
BGA792A
792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch,
40mm Square
MSX, Bus Repeater, and RapidConfigure are trademarks of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation DS500746
www.fairchildsemi.com
1 page  
Introduction (Continued)
Option 3: Registered Input with Next-Neighbor Clock as Output
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Option 4: Registered Output with Next-Neighbor Clock as Output
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Introduction (Continued)
Signal Description
RCA[8]
RCA[8] is set to a one if the I/O buffer is configured as a registered output and is assigned to use Next Neighbor
Clocking. It is zero if Next Neighbor Clocking is disabled. Next Neighbor Clocking allows the I/O buffer to be regis-
tered using the next higher numbered Port number signal as its output clock source. Port 100 on the MSX devices
can use the signal from Port 101 for its output clock if this mode is enabled. Port 531’s Next Neighbor is Port 0.
Next Neighbor Clocking will be disabled by default at reset, so RCA[8] will read as a zero.
RCA[8]
Function
0 I/O buffer not using Next Neighbor Clock in RO mode (default)
1 I/O buffer using Next Neighbor Clock in RO mode
RCA[9]
RCA[9] is set to a one if the I/O buffer is assigned to use Input Enable 1. It is zero if the I/O buffer is not using Input
Enable 1. All bi-directional I/O buffers must use one of the dedicated input enable pins (IE_0, IE_1, IE_2, or IE_3)
to enable the I/O buffer to drive data into the crosspoint array. As with the dedicated clock pins, each I/O buffer can
access two input enable signals, which will vary depending upon the quadrant of this chip in which the I/O buffer
resides. RCA[9] will read as a zero at reset.
RCA[9]
Function
0 I/O buffer not using Input Enable Source 1 (default)
1 I/O buffer using Input Enable Source 1
RCB[0] RCB[0] is set to a one if the I/O buffer is assigned to use Input Enable 2. It is zero if the I/O buffer is not using Input
Enable 2. RCB[0] will read as a zero at reset.
RCB[0]
Function
0 I/O buffer not using Input Enable Source 2 (default)
1 I/O buffer using Input Enable Source 2
RCB[1]
RCB[1] is set to a one if the I/O buffer is assigned to use Output Enable 1. It is zero if the I/O buffer is not using
Output Enable 1. All bi-directional I/O buffers must use one of the dedicated output enable pins (OE_0, OE_1,
OE_2, or OE_3) to enable the I/O buffer to drive the pin of the device. As with the dedicated clock pins, each I/O
buffer can access two output enable signals, which will vary depending upon the quadrant of the chip in which the
I/O buffer resides. RCB[1] will read as a zero at reset.
RCB[1]
Function
0 I/O buffer not using Output Enable Source 1 (default)
1 I/O buffer using Output Enable Source 1
RCB[2] RCB[2] is set to a one if the I/O buffer is assigned to use Output Enable 2. It is zero if the I/O buffer is not using
Output Enable 2. RCB[2] will read as a zero at reset.
RCB[2]
Function
0 I/O buffer not using Output Enable Source 2 (default)
1 I/O buffer using Output Enable Source 2
RCB[6:3] RCB[6:3] are reserved.
RCB[7]
RCB[7] is set to a one if the I/O buffer is configured as an inverted output. It is zero if the I/O buffer is not config-
ured as an inverted output. The output of any I/O buffer may be inverted so long as it is not a registered output or
running in Bus Repeater Mode. RCB[7] will read as a zero at reset.
RCB[7]
Function
0 I/O buffer not configured as inverted output (default)
1 I/O buffer configured as inverted output
RCB[8]
RCB[8] is set to a one if the I/O buffer is configured as a registered input and is using an inverted input clock
source. It is zero if it is not using an inverted input clock. Inputs can use any of the three clock sources described
above and may invert that clock if desired. RCB[8] will read as a zero at reset.
RCB[8]
Function
0 I/O buffer not using inverted clock source in RI mode (default)
1 I/O buffer using inverted clock source in RI mode
RCB[9]
RCB[9] is set to a one if the I/O buffer is configured as a registered output and is using an inverted output clock
source. It is zero if it is not using an inverted output clock. Outputs can use any of the three clock sources
described above and may invert that clock if desired. RCB[9] will read as a zero at reset.
RCB[9]
Function
0 I/O buffer not using inverted clock source in RO mode (default)
1 I/O buffer using inverted clock source in RO mode
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| PDF Descargar | [ Datasheet MSX532.PDF ] | |
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