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PDF KSZ8993M Data sheet ( Hoja de datos )
| Número de pieza | KSZ8993M | |
| Descripción | Integrated 3-Port 10/100 Managed Switch | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KSZ8993M/ML
Integrated 3-Port 10/100 Managed
Switch with PHYs
Rev 1.06
General Description
The KSZ8993M, a highly integrated Layer 2
managed switch, is designed for low port count,
cost-sensitive 10/100 Mbps switch systems. It offers
an extensive feature set that includes tag/port-based
VLAN, quality of service (QoS) priority,
management, management information base (MIB)
counters, MII/SNI, and CPU control/data interfaces
to effectively address both current and emerging
Fast Ethernet applications.
The KSZ8993M contains two 10/100 transceivers
with patented mixed-signal low-power technology,
three media access control (MAC) units, a high-
speed non-blocking switch fabric, a dedicated
address lookup engine, and an on-chip frame buffer
memory.
Both PHY units support 10BASE-T and 100BASE-
TX. In addition, one of the PHY unit supports
100BASE-FX.
The KSZ8993ML is the single supply version with all
the identical rich features of the KSZ8993M.
___________________________________________________________________________________________________
Functional Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2008
1
M9999-020606
1 page  
Micrel, Inc.
Revision History
Revision
1.00
1.01
1.02
Date
5/14/03
5/28/03
12/8/03
1.03 9/22/04
1.04
1.05
1.06
1.06a
4/12/05
2/14/05
2/13/07
10/28/08
KSZ8993M/ML
Summary of Changes
Created.
Added KS8993MI availability in Q4 2003.
Changed VDDIO, VDDATX and VDDARX supply voltages
from 3.3V to (3.3V or 2.5V).
Changed [PS1,PS0] = [1,1] setting from Reserved to SMI mode.
Changed Special Tagging Mode to Upstream Special Tagging Mode
(Switch port 3 to processor support only).
Updated recommended magnetic manufacturer list.
Added 25MHz crystal/oscillator clock’s ppm spec. in Pin Description.
Updated I2C Slave Serial Bus Configuration section.
Updated KSZ8993MI availability to from Q1 2004.
Added KS8993ML to General Description (page 1) and to the Functional
Description.
Updated Part Ordering Information table.
Updated pin description for pin 22 to the following:
VDDC: For KS8993M, this is an input power pin for the 1.8V digital
core VDD.
VOUT_1V8: For KS8993ML, this is an 1.8V output power pin to
supply the KS8993ML’s input power pins: VDDAP
(pin 63), VDDC (pins 91, 123), and VDDA (pins 38,
43, 57).
Updated pin description for P1LED3 (pin 25) to indicate that an external
1K pull-down is needed if a LED is connected.
Updated pin description for MDIO (pin 95) to indicate that an external
4.7K pull-up is needed if this pin is in used.
Changed the aging period from 300 +/–75 seconds to about 200 seconds.
Updated Electrical Characteristics (VIH, VIL, VOH, VOL).
Transferred to new format.
Removed references to 2.5V operation
Added reset circuit recommendation
Updated to add Pb-Free spwcifications
Add the P/N KSZ8993I into the Ordering information table
Add the P/N KSZ8993MLI into the Ordering information table
Modify the current consumption table from board to device.
October 2008
5 M9999-020606
5 Page 
Micrel, Inc.
KSZ8993M/ML
Pin Number
8
9
10
11
12
Pin Name
VDDIO
NC
NC
NC
ADVFC
13 P2ANEN
14 P2SPD
15 P2DPX
16 P2FFC
17 NC
18 NC
19 NC
20 P2LED3
21 DGND
22 VDDC/VOUT_1
V8
23 LEDSEL1
24 NC
25 P1LED3
Note:
1. P = Power supply.
Gnd = Ground.
O = Output.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Opu = Output with internal pull-up.
Type (1)
P
Ipd
Ipd
Ipu
Ipu
Ipu
Ipd
Ipd
Ipd
Opu
Ipd
Ipd
Opd
Gnd
P
Ipd
O
Opd
Description
3.3V digital VDD
No connect
No connect
No connect
1 = advertise the switch’s flow control capability via auto
negotiation.
0 = will not advertise the switch’s flow control capability via
auto negotiation.
1 = enable auto negotiation on port 2
0 = disable auto negotiation on port 2
1 = force port 2 to 100BT if P2ANEN = 0
0 = force port 2 to 10BT if P2ANEN = 0
1 = port 2 default to full duplex mode if P2ANEN = 1 and auto
negotiation fails. Force port 2 in full duplex mode if P2ANEN
= 0.
0 = port 2 default to half duplex mode if P2ANEN = 1 and
auto negotiation fails. Force port 2 in half duplex mode if
P2ANEN = 0.
1 = always enable (force) port 2 flow control feature
0 = port 2 flow control feature enable is determined by auto
negotiation result.
No connect
No connect
No connect
Port 2 LED indicator
Note: Internal pull-down is weak; it will not turn ON the LED.
See description in pin 4.
Digital ground
VDDC: For KSZ8993M, this is an input power pin for the 1.8V
digital core VDD.
VOUT_1V8: For KSZ8993ML, this is a 1.8V output power pin to
supply the KSZ8993ML’s input power pins: VDDAP (pin 63),
VDDC (pins 91 and 123), and VDDA (pins 38, 43, and 57).
LED display mode select
See description in pins 1 and 4.
No connect
Port 1 LED indicator
Note: An external 1K pull-down is needed on this pin if it is
connected to a LED. The 1K resistor will not turn ON the
LED.
See description in pin 1.
Opd = Output internal pull-down.
October 2008
11 M9999-020606
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8993M.PDF ] | |
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