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74LVQ163 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 74LVQ163은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 74LVQ163 자료 제공

부품번호 74LVQ163 기능
기능 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
제조업체 STMicroelectronics
로고 STMicroelectronics 로고


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74LVQ163 데이터시트, 핀배열, 회로
www.DataSheet4U.com
74LVQ163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ163 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVQ163M
T&R
74LVQ163MTR
74LVQ163TTR
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
parallel loading and allows all outputs to go LOW
on the next rising edge of CLOCK. A LOW signal
on LOAD overrides counting and allows
information on Parallel Data Qn inputs to be
loaded into the flip-flops on the next rising edge of
CLOCK. With LOAD and CLEAR, PE and TE
permit counting when both are high. Conversely, a
LOW signal on either PE and TE inhibits counting.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
1/13




74LVQ163 pdf, 반도체, 판매, 대치품
74LVQ163
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC Supply Voltage
-0.5 to +7
V
VI DC Input Voltage
-0.5 to VCC + 0.5
V
VO DC Output Voltage
-0.5 to VCC + 0.5
V
IIK DC Input Diode Current
± 20
mA
IOK DC Output Diode Current
± 20
mA
IO DC Output Current
± 50
mA
ICC or IGND DC VCC or Ground Current
± 300
mA
Tstg Storage Temperature
-65 to +150
°C
TL Lead Temperature (10 sec)
300 °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
4/13

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74LVQ163 전자부품, 판매, 대치품
74LVQ163
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
tPLH tPHL Propagation Delay 2.7
Time CK to Q
3.3(*)
7.5 12.0
15.0
17.0
ns
6.3 9.5
11.0 12.5
tPLH tPHL Propagation Delay 2.7
Time CK to CARRY
OUT
3.3(*)
8.8 14.0
16.0
18.5
7.1 10.5
12.0
ns
14.0
tPLH tPHL Propagation Delay 2.7
Time TE to CARRY
OUT
3.3(*)
6.1 10.0 11.5 13.0
5.2 8.0
ns
9.5 10.5
tW CK pulse Width,
(Count) High or
LOW
2.7
3.3(*)
4.0 1.9 4.0 4.0
ns
3.0 1.9 3.0 3.0
tW CK pulse Width,
(Load) High or
LOW
2.7
3.3(*)
4.0 1.9 4.0 4.0
ns
3.0 1.9 3.0 3.0
ts Setup Time HIGH 2.7
or LOW
(INPUT to CLOCK)
3.3(*)
5.0 2.5 5.0 5.0
ns
4.0 2.1 4.0 4.0
th Hold Time HIGH or 2.7
LOW
(INPUT to CLOCK)
3.3(*)
1 -1.6
1
1
ns
0.5 -1.2 0.5 0.5
ts Setup Time HIGH 2.7
or LOW (CLEAR
to CLOCK)
3.3(*)
3.0 1.5 3.0 3.0
ns
2.5 1.2 2.5 2.5
th Hold Time HIGH or 2.7
LOW (CLEAR
to CLOCK)
3.3(*)
1 -0.6
1
1
ns
0.5 -0.5 0.5 0.5
ts Setup Time HIGH 2.7
or LOW (LOAD to
CLOCK)
3.3(*)
8.0 3.7 8.0 8.0
ns
6.0 3.2 6.0 6.0
th Hold Time HIGH or 2.7
LOW (LOAD to
CLOCK)
3.3(*)
0 -3.0
0 -2.5
0
0
0
ns
0
ts Setup Time HIGH 2.7
or LOW (PE or TE
to CLOCK)
3.3(*)
7.0 3.4 7.0 7.0
ns
6.0 3.0 6.0 6.0
th Hold Time HIGH or 2.7
LOW (PE or TE
to CLOCK)
3.3(*)
0 -2.6
0 -2.2
0
0
0
ns
0
fMAX Maximum Clock
Frequency
2.7
3.3(*)
100 150
120 180
80
100
60
MHz
80
tOSLH
tOSHL
Output To Output
Skew Time
(note1, 2)
2.7
3.3(*)
0.5 1.0 1.0 1.0
0.5 1.0 1.0 1.0 ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
7/13

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관련 데이터시트

부품번호상세설명 및 기능제조사
74LVQ161

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

STMicroelectronics
STMicroelectronics
74LVQ163

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

STMicroelectronics
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