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EM434Mxxxx-xx 데이터시트 PDF




Eorex에서 제조한 전자 부품 EM434Mxxxx-xx은 전자 산업 및 응용 분야에서
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부품번호 EM434Mxxxx-xx 기능
기능 64Mb SDRAM
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EM434Mxxxx-xx 데이터시트, 핀배열, 회로
www.DataSheet4U.com
64Mb SDRAM
Ordering Information
EM 48 2M 32 4 4 V T A – 5 L
EOREX
Logo
EDO/FPM
D-RAMBUS
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
: 40
: 41
: 42
: 43
: 46
: 48
Density
16M : 16 Mega Bits
8M : 8 Mega Bits
4M : 4 Mega Bits
2M : 2 Mega Bits
1M : 1 Mega Bit
Organization
8 : x8
9 : x9
16 : x16
18 : x18
32 : x32
Refresh
1 : 1K, 8 : 8K
2 : 2K, 6 :16K
4 : 4K
Bank
2 : 2Bank 6 : 16Bank
4 : 4Bank 3 : 32Bank
8 : 8Bank
Interface
V: 3.3V
R: 2.5V
URL: http://www.eorex.com
Rev.01
F: PB free package
Power
Blank : Standard
L : Low power
I : Industrial
Min Cycle Time ( Max Freq.)
-5 : 5ns ( 200MHz )
-6 : 5ns ( 167MHz )
-7 : 7ns ( 143MHz )
-75 : 7.5ns ( 133MHz )
-8 : 8ns ( 125MHz )
-10 : 10ns ( 100MHz )
Revision
A : 1st B : 2nd
C : 3rd D :4th
G: for VGA version only
Package
C: CSP B: uBGA
T: TSOP Q: TQFP
P: PQFP ( QFP )
L: LQFP
1/33




EM434Mxxxx-xx pdf, 반도체, 판매, 대치품
Pin Descriptions ( Simplified )
64Mb SDRAM
Pin
CLK
/CS
CKE
A0 ~ A10
BA0~BA1
/RAS
/CAS
/WE
Name
System Clock
Chip select
Clock Enable
Addres s
Bank Address
Pin Function
Master Clock Input(Active on the Positive rising edge)
Selects chip when active
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
Row address (A0 to A10) is determined by A0 to A10 level
at the bank active command cycle CLK rising edge.
CA(CA0 to CA7) is determined by A0 to A7 level at the
read or write command cycle CLK rising edge.
And this column address becomes burst access start
address. A10 defines the pre-charge mode. When A10 = High
at the pre-charge command cycle, all banks are pre-charged.
But when A10 = Low at the pre-charge command cycle,
only the bank that is selected by BA is pre-charged.
Selects which bank is to be active.
Row address strobe
Column address strobe
Write Enable
Latches Row Addresses on the positive rising edge of the
CLK with /RAS “L”. Enables row access & pre-charge.
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
DQM0 ~ DQM3 Data input/output Mask
DQM controls I/O buffers.
DQ0 ~ 31
Data input/output
DQ pins have the same function as I/O pins on a conventional
DRAM.
VDD/VSS
VDDQ/VSSQ
NC
Power supply/Ground
Power supply/Ground
No connection
VDD and VSS are power supply pins for internal circuits.
VDDQ and VSSQ are power supply pins for the output buffers.
This pin is recommended to be left No Connection on the
device.
Rev.01
4/33

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EM434Mxxxx-xx 전자부품, 판매, 대치품
64Mb SDRAM
Precharge command ( /CS, /RAS, /WE = Low , / CAS = High )
CLK
/CS
/RAS
/CAS
/WE
BA
A10
CKE
Add
‘H’
This command begins precharge operation of the bank
selected by. When A10 is high,all banks are precharged,
regardless of. When BA is low,only the bank selected by
BA is precharged.
( Figure. 3 Precharged command )
Write command ( /CS, /CAS, /WE = Low, /RAS = High )
CLK
/CS
/RAS
/CAS
/WE
BA
A10
CKE
Add
‘H’
Column
If the mode register is in the burst write mode, this
command sets the burst start address given by the
column address to begin the burst write operation. The
first write data in burst mode can input with this
command with subsequent data on following clicks.
( Figure. 4 Column address and write command )
Rev.01
7/33

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부품번호상세설명 및 기능제조사
EM434Mxxxx-xx

64Mb SDRAM

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