A3P030 Datasheet PDF - Actel Corporation
| Part Number | A3P030 | |
| Description | (A3Pxxx) ProASIC3 Flash Family FPGAs | |
| Manufacturers | Actel Corporation | |
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ProASIC3 Flash Family FPGAs
Advanced v0.2
™
Features and Benefits
High Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 288 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live-At-Power-Up Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM (FROM)
Performance
• 150+ MHz Internal System Performance with 3.3 V,
66 MHz 64-bit PCI (except A3P030)
• Up to 350 MHz External System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit AES Decryption via
JTAG (IEEE1532-compliant) (except A3P030)
• FlashLock™ to Secure FPGA Contents
Low Power
• 1.5 V Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except
A3P030), and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL and LVDS (A3P250
and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable I/Os (A3P030 only)
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/Down
• IEEE1149.1 (JTAG) Boundary-Scan Test
• Pin-Compatible Packages Across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
(except A3P030)
• Six CCC Blocks Total, One with an Integrated PLL
• Flexible Phase Shift, Multiply/Divide, and Delay
Capabilities
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs (except A3P030)
• Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18 Organizations Available)
• True Dual-Port SRAM (except x18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
• Programmable Embedded FIFO Control Logic
Table 1 • ProASIC3 Product Family
System Gates
VersaTiles (D-Flip-Flops)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM (FROM) Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals1
I/O Banks
Maximum User I/Os
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
A3P030
30 k
768
–
–
1k
–
–
6
2
81
QN132
VQ100
A3P060
60 k
1,536
18
4
1k
Yes
1
18
2
96
VQ100
TQ144
FG144
A3P125
125 k
3,072
36
8
1k
Yes
1
18
2
133
A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
A3P400
400 k
9,216
54
12
1k
Yes
1
18
4
194
A3P600
600 k
13,824
108
24
1k
Yes
1
18
4
227
A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
288
VQ100
TQ144
PQ208
FG144
VQ100
PQ208
PQ208
PQ208
PQ208
FG144, FG256 FG144, FG256, FG144, FG256, FG144,
FG484
FG484
FG256, FG484
Notes:
1. Six chip (main) and three quadrant global networks are available for A3P060 and above.
2. For higher densities and support of additional features, refer to the ProASIC3E Flash FPGAs datasheet.
January 2005
© 2005 Actel Corporation
i
See Actel’s website for the latest version of the datasheet.
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Introduction and Overview
ProASIC3 Flash Family FPGAs
General Description
ProASIC3, the third-generation family of Actel Flash
FPGAs, offers performance, density, and features beyond
those of the ProASICPLUS® family. The nonvolatile Flash
technology gives ProASIC3 devices the advantage of
being a secure, low-power, single-chip solution that is
live at power-up. ProASIC3 is reprogrammable and offers
time-to-market benefits at an ASIC-level unit cost. These
features enable designers to create high-density systems
using existing ASIC or FPGA design flows and tools.
ProASIC3 devices offer 1 kbit of on-chip, user nonvolatile
FlashROM (FROM) memory storage as well as clock
conditioning circuitry based on an integrated phase-
locked loop (PLL). The A3P030 device has no PLL or RAM
support. ProASIC3 devices have up to 1 million system
gates, supported with up to 144 kbits of true dual-port
SRAM and up to 288 user I/Os.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low-unit
cost, performance, and ease of use. Unlike SRAM-based
FPGAs, the Flash-based ProASIC3 devices allow for all
functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic.
Designers can perform secure remote in-system
reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual
property (IP) cannot be compromised or copied. Secure
ISP can be performed using the industry-standard AES
algorithm. The ProASIC3 family device architecture
mitigates the need for ASIC migration at higher user
volumes. This makes the ProASIC3 family a cost-effective
ASIC replacement solution, especially for applications in
the consumer, networking/communications, computing,
and avionics markets.
Security
The nonvolatile, Flash-based ProASIC3 devices require no
boot PROM, so there is no vulnerable external bitstream
that can be easily copied. ProASIC3 devices incorporate
FlashLock, which provides a unique combination of
reprogrammability and design security without external
overhead, advantages that only an FPGA with
nonvolatile, Flash programming can offer.
ProASIC3 devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all FROM
data in the ProASIC3 devices can be encrypted prior to
loading, using the industry-leading AES-128 (FIPS192) bit
block cipher encryption standard. The AES standard was
adopted by the National Institute of Standards and
Technology (NIST) in 2000, and replaces the 1977 DES
standard. ProASIC3 devices have a built-in AES
decryption engine and a Flash-based AES key that make
them the most comprehensive programmable logic
device security solution available today. ProASIC3 devices
with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed ProASIC3 device cannot be
read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent
component of the ProASIC3 family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. ProASIC3, with
FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible. A ProASIC3 device provides the most
impenetrable security for programmable logic designs.
Advanced v0.2
1-1
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ A3P030.PDF Datasheet ] | |
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