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PDF BD3533F Data sheet ( Hoja de datos )
| Número de pieza | BD3533F | |
| Descripción | Termination Regulators | |
| Fabricantes | ROHM Semiconductor | |
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Datasheet
1.0V to 5.5V, 1A 1ch
Termination Regulators for DDR-SDRAMs
BD3533F BD3533FVM BD3533HFN
General Description
BD3533 is a termination regulator that complies with
JEDEC requirements for DDR-SDRAM. This linear power
supply uses a built-in N-channel MOSFET and high-speed
OP-AMPS specially designed to provide excellent
transient response. It has a sink/source current capability
up to 1A and has a power supply bias requirement of 3.3V
to 5.0V for driving the N-channel MOSFET. By employing
an independent reference voltage input (VDDQ) and a
feedback pin (VTTS), this termination regulator provides
excellent output voltage accuracy and load regulation as
required by JEDEC standards. Additionally, BD3533 has a
reference power supply output (VREF) for DDR-SDRAM
or for memory controllers. Unlike the VTT output that goes
to “Hi-Z” state, the VREF output is kept unchanged when
EN input is changed to “Low”, making this IC suitable for
DDR-SDRAM under “Self Refresh” state.
Key Specifications
Termination Input Voltage Range: 1.0V to 5.5V
VCC Input Voltage Range:
2.7V to 5.5V
VDDQ Reference Voltage Range: 1.0V to 2.75V
Output Voltage:
1/2 x VDDQ V (Typ)
Output Current:
BD3533F
3.0A(Max)
BD3533FVM/HFN
1.0A(Max)
High Side FET ON-Resistance:
0.4Ω(Typ)
Low Side FET ON-Resistance:
0.4Ω(Typ)
Standby Current:
0.5mA(Typ)
Operating Temperature Range: -20°C to +100°C
Packages
W(Typ) x D(Typ) x H(Max)
Features
Incorporates a Push-Pull Power Supply for
Termination (VTT)
Incorporates a Reference Voltage Circuit (VREF)
Incorporates an Enabler
Incorporates an Under Voltage Lockout (UVLO)
Incorporates a Thermal Shutdown Protector (TSD)
Compatible with Dual Channel (DDR-2)
SOP8
5.00mm x 6.20mm x 1.71mm
Applications
Power Supply for DDR 1/2/3/4 - SDRAM
Power Supply for GDDR 1/2/3/4/5 - SDRAM
Power Supply for LPDDR 1/2/3/4 - SDRAM
MSOP8
HSON8
2.90mm x 4.00mm x 0.90mm 2.90mm x 3.00mm x 0.60mm
Typical Application Circuit, Block Diagram
VCC
VDDQ
VTT_IN
VCC
6
VDDQ
5
VTT_IN
7
VCC
VCC
VCC
Reference
Block
Enable EN
2
Thermal TSD
Protection
EN
UVLO
SOFT
TSD
UVLO EN
UVLO
TSD
VCC EN
UVLO
TSD
EN
UVLO
VTT
8
3
VTTS
4
VREF
1
GND
VTT
½x
VDDQ
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product has no designed protection against radioactive rays
1/17
TSZ02201-0J1J0A900700-1-2
07.Mar.2014 Rev.001
1 page  
BD3533F BD3533FVM BD3533HFN
Typical Performance Curves
Datasheet
1.252
1.251
1.25
1.249
1.248
-10
-5 0
IRIREEFF ((mmAA))
5
Figure 1. Output Voltage vs IREF
(DDR-1)
10
0.902
0.901
0.9
0.899
0.898
0.897
-10
-5 0
IRIREEFF (mmAA))
5
Figure 2. Output Voltage vs IREF
(DDR-2)
10
1.258
1.256
1.254
1.252
1.250
1.248
1.246
1.244
-2
-1 0
1
Output CIuTrrTe(nAt :)ITT (A)
2
Figure 3. Termination Output Voltage vs Output Current
(DDR-1)
00.9.9112
00.9.9110
00.9.9008
00.9.9006
00.9.9004
00.9.9002
00.9.9000
00.8.8998
00.8.8996
-2
-1 0 1
Output CuITrrTe(nAt ): ITT (A)
2
Figure 4. Termination Output Voltage vs Output Current
(DDR-2)
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/17
TSZ02201-0J1J0A900700-1-2
07.Mar.2014 Rev.001
5 Page 
BD3533F BD3533FVM BD3533HFN
Datasheet
Operational Notes – continued
12. Regarding Input Pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Figure 13. Example of Monolithic IC Structure
13. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be
within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below the
TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
The present IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C
(standard value) and has a -15°C (standard value) hysteresis width.
14. Capacitor Across Output and GND
If a large capacitor is connected between the output pin and ground pin, current from the charged capacitor can flow into
the output pin and may destroy the IC when the VCC or VTT_IN pin is shorted to ground or pulled down to 0V. Use a
capacitor smaller than 1000µF between output and ground.
15. Output Capacitor (C1)
Do not fail to connect a output capacitor to VREF output terminal for stabilization of output voltage. The capacitor
connected to VREF output terminal works as a loop gain phase compensator. Insufficient capacitance may cause an
oscillation. It is recommended to use a low temperature coefficient 1-10 μF ceramic capacitor, though it depends on
ambient temperature and load conditions. It is therefore requested to carefully check under the actual temperature and
load conditions to be applied.
16. Output Capacitor (C4)
Do not fail to connect a capacitor to VTT output pin for stabilization of output voltage. This output capacitor works as a
loop gain phase compensator and an output voltage variation reducer in the event of sudden change in load.
Insufficient capacitance may cause an oscillation. And if the equivalent series resistance (ESR) of this capacitor is high,
the variation in output voltage increases in the event of sudden change in load. It is recommended to use a 47-220 μF
functional polymer capacitor, though it depends on ambient temperature and load conditions. Using a low ESR ceramic
capacitor may reduce a loop gain phase margin and cause an oscillation, which may be improved by connecting a
resistor in series with the capacitor. It is therefore requested to carefully check under the actual temperature and load
conditions to be applied.
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/17
TSZ02201-0J1J0A900700-1-2
07.Mar.2014 Rev.001
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet BD3533F.PDF ] | |
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