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PDF BD8105FV Data sheet ( Hoja de datos )
| Número de pieza | BD8105FV | |
| Descripción | LED driver | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Power Management IC Series for Automotive Body Control
LED Driver
BD8105FV
No.09039EBT01
●Description
The BD8105FV is a serial parallel control LED driver with 35V input voltage rating.
Responding to the 3-line serial data, it turns the 12ch open drain output on/off.
Due to its compact size, it is optimal for small spaces.
●Features
1) Open Drain Output
2) 3-line Serial Control + Enable Signal
3) Internal Temperature Protection Circuit (TSD)
4) Cascade Connection Compatible
5) SSOP-B20W
6) Internal 12ch Power Transistor
Applications
These ICs can be used with car and consumer electronic.
●Absolute Maximum Ratings (Ta=25℃)
Item
Symbol
Value
Unit
Power Supply Voltage
VCC
7
V
Output Voltage（Pin No : 4～9, 11～16）
VDmax
35
V
Input Voltage（Pin No : 1, 2, 3, 17, 18）
VIN -0.3～VCC
V
Power Dissipation
Pd
1187*
mW
Operating Temperature Range
Topr -40～+105
℃
Storage Temperature Range
Tstg -55～+150
℃
Drive Current (DC)
IomaxD
50
mA
Drive Current（Pulse）
IomaxP
150**
mA
Junction Temperature
Tjmax
150
℃
* Pd decreased at 9.50mW/℃ for temperatures above Ta=25℃,mounted on 70×70×1.6mm Glass-epoxy PCB.
** Do not however exceed Pd. Time to impress≦200msec
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/12
2009.07 - Rev.B
1 page  
BD8105FV
Technical Note
●Block Operation
1）Serial I/F
The I/F is a 3-line serial (LATCH, CLK, SERIN) style.
12-bit output ON/OFF can be set-up. This is composed of shift register. + 12-bit register.
2）Driver
It is a 12-bit open drain output.
3）TSD (Thermal Shut Down)
To prevent heat damage and overheating, when the chip temperature goes over approximately 175℃, the output turns
off. When the temperature goes back down, normal operation resumes. However, the intended use of the
temperature protection circuit is to protect the IC, so please construct thermal design with the junction temperature
Tjmax under 150℃.
●Application Circuit
VCC
10uF
VBAT
10uF
Micro-
computer
VCC
SDWN
LATCH
RST_B
CLK
SERIN
SEROUT
GND
D0
D1
D2
D3
D4
D5
D6
DD78
D9
D10
D11
VCC
10uF
VCC
SDWN
LATCH
RST_B
CLK
SERIN
SEROUT
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Fig.12
↓IF
Rres
VF
IF= VBAT - VF
Rres + RON
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
5/12
2009.07 - Rev.B
5 Page 
BD8105FV
Technical Note
●Operation Notes
(1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in
IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is
suffered.
A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute
maximum ratings may be exceeded is anticipated.
(2) Reverse connection of a power supply connector
If the connector of power is wrong connected, it may result in IC breakage. In order to prevent the breakage from the wrong
connection, the diode should be connected between external power and the power terminal of IC as protection solution.
(3) GND potential
Ensure a minimum GND pin potential in all operating conditions.
(4) Setting of heat
Use a setting of heat that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
(5) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature
range may result in IC damage.
(6) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
(7) Thermal shutdown circuit(TSD)
This IC built-in a Thermal shutdown circuit (TSD circuit). If Chip temperature becomes 175 (TYP.), make the output an Open
state. Eventually, warmly clearing the circuit is decided by the condition of whether the heat excesses over the assigned limit,
resulting the cutoff of the circuit of IC, and not by the purpose of preventing and ensuring the IC. Therefore, the warm
switch-off should not be applied in the premise of continuous employing and operation after the circuit is switched on.
(8) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and
use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process
(9) IC terminal input
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions
are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.
For example, when a resistor and transistor are connected to pins. (See the chart below.)
the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other
adjacent elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's
architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage.
For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements,
such as by the application of voltages lower than the GND (PCB) voltage to input pins.
(Pin A)
Resistor
(Pin B)
Transistor (NPN)
B
CE
(Pin B)
BC
P+
N
P
N
P+
N
P Parasitic elements
GND
(10) Ground wiring patterns
P+
N
N
P
N
GND
P+
N
P substrate
Parasitic elements
GND
(Pin A)
E
GND
Parasitic
elements
Parasitic
elements
GND
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a
single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by
large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any
external components.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
11/12
2009.07 - Rev.B
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet BD8105FV.PDF ] | |
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