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PDF 56F8335 Data sheet ( Hoja de datos )
| Número de pieza | 56F8335 | |
| Descripción | (56F8135 / 56F8335) 16-bit Digital Signal Controller | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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56F8335/56F8135
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controller
MC56F8335
Rev. 1
12/2005
freescale.com
1 page  
56F8335/56F8135 Features
Part 1 Overview
1.1 56F8335/56F8135 Features
1.1.1 Core
• Efficient 16-bit 56800E family controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8335 and 56F8135 devices.
Table 1-1 Device Differences
Feature
56F8335
Guaranteed Speed
Program RAM
Data Flash
60MHz/60 MIPS
4KB
8KB
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
2x6
1
4
2x4
1
56F8135
40MHz/40MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
Freescale Semiconductor
Preliminary
56F8335 Technical Data, Rev. 1
5
5 Page 
Architecture Block Diagram
To/From IPBus Bridge
CLKGEN
(OSC / PLL)
Timer A
4 Quadrature Decoder 0
4 Timer D
Timer B
4 Quadrature Decoder 1
Interrupt
Controller
Low-Voltage Interrupt
POR & LVI
System POR
SIM RESET
COP Reset
COP
FlexCAN
2
SPI1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
4 SPI0
2 SCI0
2 SCI1
IPBus
NOT available on the 56F8135 device.
PWMA
PWMB
13
SYNC Output
13
SYNC Output
ch3i
ch3o
ch2i
Timer C
ch2o
2
ADCB
8
ADCA
8
TEMP_SENSE 1
Note: ADC A and ADC B use the same
voltage reference circuit with VREFH,
VREFP, VREFMID, VREFN, and VREFLO
pins.
Figure 1-2 Peripheral Subsystem
Freescale Semiconductor
Preliminary
56F8335 Technical Data, Rev. 1
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet 56F8335.PDF ] | |
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