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PDF 56F8345 Data sheet ( Hoja de datos )
| Número de pieza | 56F8345 | |
| Descripción | (56F8145 / 56F8345) 16-bit Digital Signal Controllers | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
56F8345/56F8145
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8345
Rev. 17
01/2007
freescale.com
1 page  
56F8345/56F8145 General Description
Note: Features in italics are NOT available in the 56F8145 device.
www.DataSheet4U.com
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Up to two Quadrature Decoders
• FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
6 PWM Outputs
3 Current Sense Inputs
or GPIOC
4 Fault Inputs
PWMA
6 PWM Outputs
3 Current Sense Inputs
or GPIOD
4 Fault Inputs
PWMB
4 AD0
4
ADCA
AD1
Memory
5 VREF
Program Memory
4 AD0
64K x 16 Flash
ADCB
2K x 16 RAM
4 AD1
4K x 16 Boot
Flash
TEMP_SENSE
Quadrature Data Memory
4 Decoder 0 or 4K x 16 Flash
Quad
4K x 16 RAM
Timer A or
GPIOC
Quadrature
4 Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC Decoding
2 Quad Timer Peripherals
C or GPIOE
4 Quad Timer
D or GPIOE
2 FlexCAN
SPI0 or
GPIOE
RSTO
RESET
5
VPP
2
OCR_DIS
VCAP VDD VSS VDDA
47
52
VSSA
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Program Controller
Address
and Hardware Generation Unit
Looping Unit
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
* External
Address Bus
Switch
6
5
* External
Data
Bus Switch
4
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
D7-10 or GPIOF0-3
IPBus Bridge (IPBB)
* Bus
Control
6
GPIOD0-5 or CS2-7
Peripheral
Device Selects
RW IPAB IPWDB
Control
IPRDB
Clock
resets
PLL
* EMI not functional in
this package; use as
GPIO pins
SCI1 or SCI0 or COP/ Interrupt
GPIOD GPIOE Watchdog Controller
System
P
O
Integration R
Module
Clock O
Generator
S
C
XTAL
EXTAL
4 22
IRQA IRQB
CLKO
CLKMODE
56F8345/56F8145 Block Diagram - 128 LQFP
Freescale Semiconductor
Preliminary
56F8345 Technical Data, Rev. 17
5
5 Page 
Award-Winning Devewlowpwm.eDnattaESnheveirto4Unm.coemnt
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. The PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1
to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters
through two channels of Quad Timer C.
The 56F8145 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase
inputs, permitting generation of a number proportional to actual position. Speed computation capabilities
accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder
can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered
to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller is also a part of the 56F8145.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
Freescale Semiconductor
Preliminary
56F8345 Technical Data, Rev. 17
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 56F8345.PDF ] | |
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