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56F8366 데이터시트 PDF




Freescale Semiconductor에서 제조한 전자 부품 56F8366은 전자 산업 및 응용 분야에서
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부품번호 56F8366 기능
기능 (56F8166 / 56F8366) 16-bit Digital Signal Controllers
제조업체 Freescale Semiconductor
로고 Freescale Semiconductor 로고


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56F8366 데이터시트, 핀배열, 회로
www.DataSheet4U.com
56F8366/56F8166
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8366
Rev. 6
01/2007
freescale.com




56F8366 pdf, 반도체, 판매, 대치품
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8366/56F8166 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment. . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 14
Part 2: Signal/Connection Descriptions . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 3: On-Chip Clock Synthesis (OCCS) . 38
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 40
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map. . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 44
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 47
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 49
4.7. Peripheral Memory Mapped Registers . . . . 50
4.8. Factory Programmed Memor. . . . . . . . . . . . 82
Part 5: Interrupt Controller (ITCN) . . . . . . . . 83
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3. Functional Description . . . . . . . . . . . . . . . . . 83
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 85
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 85
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 86
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Part 6: System Integration Module (SIM) . 114
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 115
6.4. Operating Mode Register . . . . . . . . . . . . . 116
6.5. Register Descriptions . . . . . . . . . . . . . . . . 117
6.6. Clock Generation Overview . . . . . . . . . . . 132
6.7. Power-Down Modes Overview . . . . . . . . . 132
6.8. Stop and Wait Mode Disable Function . . . 133
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Part 7: Security Features . . . . . . . . . . . . . . 134
7.1. Operation with Security Enabled . . . . . . . 134
7.2. Flash Access Blocking Mechanisms . . . . . 134
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 137
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 137
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 137
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 137
Part 9: Joint Test Action Group (JTAG) . . 142
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 142
Part 10: Specifications . . . . . . . . . . . . . . . 143
10.1. General Characteristics . . . . . . . . . . . . . . 143
10.2. DC Electrical Characteristics. . . . . . . . . . 147
10.3. AC Electrical Characteristics . . . . . . . . . . 151
10.4. Flash Memory Characteristics. . . . . . . . . 151
10.5. External Clock Operation Timing . . . . . . . 152
10.6. Phase Locked Loop Timing . . . . . . . . . . . 152
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 153
10.8. External Memory Interface Timing . . . . . . 153
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . 156
10.10. Serial Peripheral Interface
(SPI) Timing . . . . . . . . . . . . . . . . . 158
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 161
10.12. Quadrature Decoder Timing . . . . . . . . . 162
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . . 163
10.14. Controller Area Network (CAN) Timing . 163
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 164
10.16. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . 165
10.17. Equivalent Circuit for ADC Inputs . . . . . 168
10.18. Power Consumption . . . . . . . . . . . . . . . 168
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 170
11.1. 56F8366 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 170
11.2. 56F8166 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 173
Part 12: Design Considerations . . . . . . . . 177
12.1. Thermal Design Considerations . . . . . . . . 177
12.2. Electrical Design Considerations . . . . . . . 178
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . 179
Part 13: Ordering Information . . . . . . . . . 180
56F8366 Technical Data, Rev. 6
4 Freescale Semiconductor
Preliminary

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56F8366 전자부품, 판매, 대치품
Device Description
• Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
• Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO
lines)
— In the 56F8366, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
— In the 56F8166, SPI1 can alternately be used only as GPIO
• Computer Operating Properly (COP) / Watchdog timer
• Two dedicated external interrupt pins
• 62 General Purpose I/O (GPIO) pins
• External reset input pin for hardware reset
• External reset output pin for system reset
• Integrated Low-Voltage Interrupt module
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
• Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.5 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8366 and 56F8166 are members of the 56800E core-based family of controllers. Each combines,
on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a
microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because
of its low cost, configuration flexibility, and compact program code, the 56F8366 and 56F8166 are
well-suited for many applications. The devices include many peripherals that are especially useful for
motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and
control, automotive control (56F8366 only), engine management, noise suppression, remote utility
metering, industrial control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8366 and 56F8166 support program execution from either internal or external memories. Two
data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also
provides two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
Freescale Semiconductor
Preliminary
56F8366 Technical Data, Rev. 6
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
56F8365

(56F8365 / 56F8165) 16-bit Digital Signal Controllers

Freescale Semiconductor
Freescale Semiconductor
56F8366

(56F8166 / 56F8366) 16-bit Digital Signal Controllers

Freescale Semiconductor
Freescale Semiconductor

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