PDF MC33689D Data sheet ( Hoja de datos )

Número de pieza	MC33689D
Descripción	System Basis Chip
Fabricantes	Freescale Semiconductor
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No Preview Available ! www.DFaretaeSshceeatl4eUS.ceommiconductor Technical Data System Basis Chip with LIN Transceiver Document Number: MC33689 Rev. 7.0, 8/2006 33689D The 33689 is a SPI-controlled System Basis Chip (SBC) that combines many frequently used functions in an MCU-based system plus a Local Interconnect Network (LIN) transceiver. Applications include power window, mirror, and seat controls. The 33689 has a 5.0 V, 50 mA low dropout regulator with full protection and reporting features. The device provide full SPI-readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN transceiver waveshaping circuitry can be disabled for higher data rates. One 50 mA and two 150 mA high-side switches with output protection are available to drive inductive or resistive loads. The 150 mA switches can be pulse-width modulated (PWM). Two high-voltage inputs are available for contact monitoring or as external wake-up inputs. A current sense operational amplifier is available for load current monitoring. The 33689 has three operational modes: • Normal (all functions available) • Sleep (VDD OFF, wake-up via LIN bus or wake-up inputs) • Stop (VDD ON, wake-up via MCU, LIN bus, or wake-up inputs) SYSTEM BASIS CHIP WITH LIN DWB SUFFIX EW SUFFIX (PB-FREE) 98ARH99137A 32-PIN SOICW Features • Full-Duplex SPI Interface at Frequencies up to 4.0 MHz • LIN Transceiver Capable to 100 kbps with Waveshaping Capability • 5.0 V Low Dropout Regulator Full Fault Detection and Protection • One 50 mA and Two 150 mA Protected High-Side Switches • Current Sense Operational Amplifier • The 33689 is compatible with LIN 2.0 Specification Package. • Pb-Free Packaging Designated by Suffix Code EW ORDERING INFORMATION Device MC33689DDWB/R2 MCZ33689DEW/R2 Temperature Range (TA) -40°C to 125°C Package 32 SOICW VDD VPWR 33689 VS1 HS3 VS2 5.0 V VCC L1 VDD L2 WDC CS CS MCU SCK MOSI SPI SCLK MOSI MISO MISO INT RST IN OUT TXD RXD HS1 HS2 E+ E- GND TGND AGND LIN BUS Figure 1. 33689 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006. All rights reserved. 1 page ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS VPWR Supply Voltage at VS1 and VS2 Continuous Transient (Load Dump) VSUPDC VSUPTR -0.3 to 27 40 V Supply Voltage at VDD and VCC Output Current at VDD Logic Input Voltage at MOSI, SCLK, CS, IN, and TXD Logic Output Voltage at MISO, INT, RST, and RXD Input Voltage at E+ and E- Input Current at E+ and E- Output Voltage at OUT Output Current at OUT Input Voltage at L1 and L2 DC Input with a 33 kΩ Resistor Transient Input with External Component (per ISO7637 Specification) (See Figure 4, page 6) Input/Output Voltage at LIN DC Voltage Transient Input Voltage with specified External Component (per ISO7637 Specification) (See Figure 4, page 6) DC Output Voltage at HS1 and HS2 Positive Negative DC Output Voltage at HS3 ESD Voltage, Human Body Model (1) GND Configured as Ground. TGND and AGND Configured as I/O Pins LIN, L1, and L2 All Other Pins ESD Voltage, Charge Device Model (1) Corner Pins (Pins 1, 16, 17, and 32) All other Pins (Pins 2–15 and 18–31) VDD IDD VINLOG VOUTLOG VE+ / VE- IE+ / IE- VOUT IOUT VLXDC VLXTR VBUSDC VBUSTR VHS+ VHS- VHS3 VESD1 VESD2 -0.3 to 5.5 Internally Limited -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to 7.0 ± 20 -0.3 to VCC+0.33 ± 20 -18 to 40 ±100 -18 to 40 -150 to 100 VVS2 + 0.3 Internally Clamped -0.3 to VVS2 + 0.3 ± 4000 ± 2000 ± 750 ± 500 V A V V V mA V mA V V V V V V Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Charge Device Model, Robotic (CZAP =4.0 pF). Analog Integrated Circuit Device Data Freescale Semiconductor 33689 5 5 Page ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit RXD OUTPUT PIN (LIN PHYSICAL LAYER) Low-Level Output Voltage IOUT ≤ 1.5 mA High-Level Output Voltage IOUT ≤ 250 µA TXD INPUT PIN (LIN PHYSICAL LAYER) VOL VOH V 0.0 — 0.9 V 3.75 — 5.25 Low-Level Input Voltage High-Level Input Voltage Input Hysteresis Pullup Current Source 1.0 V < VTXD < 3.5 V LIN PHYSICAL LAYER, TRANSCEIVER VIL — — 1.5 V VIH 3.5 — — V VINHYS 50 145 300 mV IPUTXD µA -100 — - 20 Transceiver Output Voltage Dominant State, TXD LOW, External Bus Pullup 500 Ω Recessive State, TXD HIGH, IOUT = 1.0 µA V VLINDOM — — 1.4 VLINREC VSUP -1.0 — — Pullup Resistor to VSUP In Normal Mode and in Sleep and Stop Modes When Not Disabled by SPI RPU kΩ 20 30 47 Pullup Current Source In Sleep and Stop Modes When Pullup Disabled by SPI IPULIN µA — 1.3 — Output Current Shutdown Threshold IOUTSD 50 75 150 mA Leakage Output Current to GND VS1 and VS2 Disconnected, VLIN = 18 V Recessive State, 8.0 V < VSUP < 18 V, 8.0 V < VLIN < 18 V GND Disconnected, VGND = VSUP, VLIN = -18 V IBUSLEAK — 1.0 10 µA 0.0 3.0 20 µA -1.0 — 1.0 mA LIN PHYSICAL LAYER, RECEIVER Receiver Input Threshold Voltage Dominant State, TXD HIGH, RXD LOW Recessive State, TXD HIGH, RXD HIGH Center (VBUSDOM -VBUSREC)/ 2 Hysteresis (VBUSDOM -VBUSREC) Bus Wake-Up Threshold VSUP VBUSDOM 0.0 — 0.4 VBUSREC 0.6 — 1.0 VBUSCNT 0.475 0.5 0.525 VBUSHYS — — 0.175 VBUSWU — 0.5 — VSUP Analog Integrated Circuit Device Data Freescale Semiconductor 33689 11 11 Page

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