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PDF MCZ33793A Data sheet ( Hoja de datos )
| Número de pieza | MCZ33793A | |
| Descripción | Distributed System Interface (DSI) Sensor Interface | |
| Fabricantes | Freescale Semiconductor | |
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Technical Data
Distributed System Interface
(DSI) Sensor Interface
The 33793 is a slave Distributed System Interface (DSI) device
that is optimized as a sensor interface. The device contains circuits
to power sensors such as accelerometers and to digitize the analog
level from the sensor. The device is controlled by commands over the
DSI bus and returns measured data over the bus.
Features
• Conforms to DSI Specification Version 1
• 4-Channel, 8-Bit Analog-to-Digital Converter (ADC)
• 4 Pins Configurable as Analog or Logic Inputs or as Logic
Outputs
• Provides Regulated +5.0 V Output for Sensor Power from Bus
• Additional High-Drive Logic Output
• Undervoltage Fault Detection and Signaling
• On-Board Clock (No External Elements Required)
• Field-Programmable Address
• Default and Field-Programmable as a DSI Daisy Chain Device
• Recognizes Reverse Initialization for Open Bus Fault Tolerance
• Detects Short to Battery on Bus Switch and Prevents Its Closure
• Pb-Free Packaging Designated by Suffix Code EF
Document Number: MC33793
Rev 13.0, 11/2006
33793/A
DISTRIBUTED SYSTEM INTERFACE
SCALE 2:1
D SUFFIX
EF SUFFIX (Pb-FREE)
98ASB42566B
16-PIN SOICN
ORDERING INFORMATION
Device
MC33793D/R2
Temperature
Range (TJ)
Package
MCZ33793EF/R2 -40°C to 150°C
16 SOICN
MCZ33793AEF/R2
33790
GND
DSIO
X-Y
Accelerometer
Error
Test
X
Y
VCC
GND
33793
BUSIN
BUSRTN
I/O0
I/O1
I/O2
I/O3 BUSOUT
H_Cap
REGOUT
LOGOUT
AGND
Multiple
DSI Slaves
33793
BusIN
Figure 1. 33793 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
1 page  
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
I/O Pin Voltage
I/O Pin Current
BUSIN, BUSOUT, BUSRTN, and H_CAP Voltage
BUSIN, BUSOUT, BUSRTN, and H_CAP Current (Continuous)
ESD Protection (1)
Human Body Model
Machine Model
THERMAL RATINGS
VIO
IIO
VIN
IIN
VESD1
VESD2
-0.3 to VREGOUT + 0.5
5.0
-0.3 to 40
250
±2000
±200
V
mA
V
mA
V
Storage Temperature
TSTG
-55 to 150
°C
Operating Junction Temperature
Peak Package Reflow Temperature During Reflow (2), (3)
TJ
TPPRT
-40 to 150
Note 3.
°C
°C
Thermal Resistance Junction to Case
RθJC
150 °C/W
Notes
1. ESD1 performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 performed in accordance with the
Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33793
5
5 Page 
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
part is reset. The purpose of this is to allow the part to reset
itself if the connection to the master is lost or if power is
removed from the system.
5.0 V REGULATOR
The 5.0 V regulator supplies internal power for the device
and also provides approximately 6.0 mA through the
REGOUT pin to power an external sensor.
UNDERVOLTAGE DETECTOR
The undervoltage detector monitors the output voltage of
the 5.0 V regulator. If the REGOUT voltage drops too low for
accurate A/D operation, a signal is sent to the control logic.
The control logic will interpret this signal and, in response to
a command, report a status indicating an undervoltage
condition to have existed. When received, the command will
clear the signal after having read the status. If the voltage is
too low when the A/D conversion was completed, the
returned value will be zero (binary 00000000).
IO PINS 0 TO 3
The IO pins can serve as logic inputs, logic outputs, or
analog inputs. At power-up or after a clear, the pins are all
logic inputs and can be used to measure an analog level
value for an analog value request command. The pins can be
individually configured as logic inputs or outputs by the IO
Control command. If the pin is configured as a logic output,
reading the analog value will return the analog level the
output is being driven to.
ANALOG-TO-DIGITAL CONVERTER
The ADC is an 8-bit successive approximation type using
on-board capacitive division. It uses the Clk signal from the
on-board oscillator for sequencing.
The ADC uses REGOUT as a full-scale reference voltage
and ground AGND for a zero-level reference.
The ADC signals when it has made a valid conversion by
asserting a signal to the controller. If this signal is not
asserted when a value is being captured by the controller, the
controller will signal that an invalid A/D value was obtained.
The value of “0" (binary 00000000) is reserved by the
control logic to signal an error. A value of “0” from the ADC
will be reported as “1” (binary 00000001) by the control logic.
SERIAL ENCODER
The Serial Encoder accepts the digitized value from the
ADC and formatting/data from the Control Logic. A logic
transition from Idle to Signal High and then to Signal Low at
BUSIN will cause the first bit to be presented to the current
switch (Response Loading). A transition to Signal High and
back to Signal Low will cause the next bit to be presented to
the current switch. This will continue until a transition back to
Idle turns off the current switch.
SLEW
The slew circuit serves to reduce EMI produced as a result
of switching the bus loading current sink element. The slew
Analog Integrated Circuit Device Data
Freescale Semiconductor
circuit limits the rise and fall time of current loading the bus by
controlling the current sinking element.
SWITCHED CURRENT SOURCE
A "1" data return bit will be signaled by turning on a fixed
current source. During signaling time, the 33793 will be using
power from H_CAP and not loading the bus for power. The
current will be drawn from either BUSIN or BUSOUT or split
between them. The split can be in any proportion as long as
the total is correct.
The current source is turned off whenever the bus is at Idle
level.
LEVEL DETECTOR
The level detector contains comparators to determine if
the BUSIN or BUSOUT is at idle, logic high, or logic low. The
inputs from BUSIN and BUSOUT are sensed by the device
so that if either side is driven by the signaling waveform while
the other is not, the signaling will be detected. This circuit also
provides a signal to indicate if the signal is being received on
the BUSOUT pin. If a "reverse initialization" command is
received, it can only be acted upon if the device is not already
initialized and if the signal is present on BUSOUT.
SERIAL DECODER
The Serial Decoder monitors transitions on the BUSIN or
BUSOUT. When the 33793 is Idle and supplying power to
itself and the external device(s) (via REGOUT), the input to
BUSIN will be in the Idle state. A transition from this level to
Signal Low (through Signal High) will start the process of
decoding a word of data. BUSIN is driven from Signal Low to
Signal High for each bit and back to Signal Low to start the
next bit. The determination of whether the bit was a one or a
zero is made by determining whether it spent more time low
(a zero) or high (a one). The end of the word is signaled by a
transition at the end of the last bit from Signal High to Idle.
The advantage of this method is that it will accept data over
a wide range of rates and is not dependent on an accurate
clock.
The controller will typically indicate a logic zero by
spending 2/3 of the bit period at Signal Low and 1/3 at Signal
High. A logic one would be 1/3 of the bit period at Signal Low
and 2/3 at Signal High.
CONTROL LOGIC
The control logic performs the digital operations carried
out by this device. Its principle functions include:
• Decoding input instructions.
• Control the general purpose I/O and LOGICOUT in
response to BUSIN or BUSOUT commands.
• Control A/D conversions.
• Form response word.
• Capture and store address.
• Control BUSSW.
• Reset device on power-up.
• Control the general purpose I/O logic configuration.
33793
11
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