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PDF V385A Data sheet ( Hoja de datos )
| Número de pieza | V385A | |
| Descripción | 8-BIT LVDS TRANSMITTER | |
| Fabricantes | ICS | |
| Logotipo |  |
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V385A
8-BIT LVDS TRANSMITTER FOR VIDEO
General Description
The V385A transmitter converts 28 bits of 3.3 V
CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link.
Compared to the V385, the V385A provides an
extended clock frequency range of 12-90 MHz, rather
than 20-85 MHz. Other performance improvements
have been incorporated as well.
The V385A can be programmed for rising edge or
falling edge clocks through pin R_FB.
Pin Assignment
VCC
TxIN5
TxIN6
TxIN7
GND
TxIN8
TxIN9
TxIN10
VCC
TxIN11
TxIN12
TxIN13
GND
TxIN14
TxIN15
TxIN16
R_FB
TxIN17
TxIN18
TxIN19
GND
TxIN20
TxIN21
TxIN22
TxIN23
VCC
TxIN24
TxIN25
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
56-pin TSSOP
TxIN4
TxIN3
TxIN2
GND
TxIN1
TxIN0
TxIN27
LVDS_GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
LVDS_VCC
LVDS_GND
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
TxCLKIN
TxIN26
GND
Features
• Extended clock frequency range of 12 to 90 MHz
• Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83, but with extended clock frequency
and operating temperature range
• Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
• Up to 2.52 Gbps throughput or 315 Megabytes/sec
bandwidth
• Spread spectrum compatible
• Supports SD, HD and VGA graphics applications
• LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Single 3.3 V low-power CMOS design
• Operating temperature of 0 to +70°C
• Programmable rising or falling edge strobe
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
Red, Green, Blue 24
HSYNC
VSYNC
DATA ENABLE
CONTROL
R_FB
PWRDWN
CLOCK
TTL to
LVDS
PLL
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
V385A Datasheet
1
11/23/05
Revision 0.1
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com
1 page  
V385A
8-BIT LVDS TRANSMITTER FOR VIDEO
Parameter
Symbol
Conditions
Recommended Transmitter Input Characteristics
TxCLK IN Transition Time
TCIT
TxCLK IN Period
TCIP
TxCLK IN High Time
TCIH
TxCLK IN Low Time
TCIL
TxIN Transition Time
TXIT
Transmitter Switching Characteristics
LVDS Low-to-High Time
LLHT
LVDS High-to-Low Time
LHLT
Transmitter Output Pulse
Position
TPPos0 Bit0
TPPos1 Bit1
TPPos2 Bit2
TPPos3 Bit3
TPPos4 Bit4
TPPos5 Bit5
TPPos6 Bit6
Transmitter Phase Loop Set TPLLS
TxIN Setup to TxCLK IN
TSTC
TxIN Hold to TxCLK IN
THTC
TxCLK IN to TxCLK OUT
Delay
TCCD
Min. Typ. Max. Units Freq.
11.11
0.35T
0.35T
1.5
T
0.5T
0.5T
5
83.333
0.65T
0.65T
6
ns
ns
ns
ns
ns
-0.2
T/7-0.2
2T/7-0.2
3T/7-0.2
4T/7-0.2
5T/7-0.2
6T/7-0.2
2.5
0.5
10
0.75
0.75
0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
1.4
1.4
0.2
T/7+0.2
2T/7+0.2
3T/7+0.2
4T/7+0.2
5T/7+0.2
6T/7+0.2
10
30
ns
ns
ns 85 MHz
ns 85 MHz
ns 85 MHz
ns 85 MHz
ns 85 MHz
ns 85 MHz
ns 85 MHz
ms
ns
ns
ns
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Symbol
θJA
θJA
θJA
θJC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
84
76
67
50
Max.
Units
°C/W
°C/W
°C/W
°C/W
V385A Datasheet
5
11/23/05
Revision 0.1
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet V385A.PDF ] | |
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