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PDF 33926 Data sheet ( Hoja de datos )
| Número de pieza | 33926 | |
| Descripción | 5.0A Throttle Control H-Bridge | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
5.0 A Throttle Control H-Bridge
The 33926 is a SMARTMOS monolithic H-Bridge Power IC
designed primarily for automotive electronic throttle control, but is
applicable to any low-voltage DC servo motor control application
within the current and voltage limits stated in this specification.
The 33926 is able to control inductive loads with currents up to
5.0 A peak. RMS current capability is subject to the degree of
heatsinking provided to the device package. Internal peak-current
limiting (regulation) is activated at load currents above 6.5 A 1.5 A.
Output loads can be pulse width modulated (PWM’ed) at frequencies
up to 20 kHz. A load current feedback feature provides a proportional
(0.24% of the load current) current output suitable for monitoring by a
microcontroller’s A/D input. A Status Flag output reports
undervoltage, overcurrent, and overtemperature fault conditions.
Two independent inputs provide polarity control of two half-bridge
totem-pole outputs. Two independent disable inputs are provided to
force the H-Bridge outputs to tri-state (high-impedance off state). An
inverted input changes the IN1 and IN2 inputs to LOW = true logic.
Features
• 5.0 to 28 V continuous operation (transient operation from 5.0 to
40 V)
• 225 m maximum RDS(on) at 150 °C (each H-Bridge MOSFET)
• 3.0 V and 5.0 V TTL / CMOS logic compatible inputs
• Overcurrent limiting (Regulation) via an internal constant-off-time
PWM
• Output short-circuit protection (short to VPWR or ground)
• Temperature dependent current limit threshold reduction
• All Inputs have an internal source/sink to define the default (floating
input) states
• Sleep mode with current draw < 50 µA (with inputs floating or set to
match default logic states)
Document Number: MC33926
Rev. 10.0, 8/2014
33926
AUTOMOTIVE THROTTLE H-BRIDGE
ACTUATOR/ MOTOR EXCITER
BoStCtoAmLE V2:i1ew
PNB SUFFIX (Pb-FREE)
98ARL10579D
32-PIN PQFN
Applications
• Electronic Throttle Control (ETC)
• Exhaust Gas Recirculation (EGR)
• Turbo Flap Control
• Industrial and Medical pumps and motor control
VDD
VPWR
MCU
33926
SF VPWR
FB CCP
IN1 OUT1
IN2
INV
SLEW
D1
OUT2
D2 PGND
EN AGND
MOTOR
Figure 1. 33926 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2007 - 2014. All rights reserved.
1 page  
PIN CONNECTIONS
Table 2. 33926 Pin Definitions (continued)
Pin
Pin Name
Pin
Function
Formal Name
Definition
12, 13,
14, 15
16
18 – 20,
22 – 24
21
26
27, 28,
29, 30
32
OUT1
D2
PGND
SF
D1
OUT2
CCP
Power
Output
Logic Input
H-Bridge Output 1
Disable Input 2
(Active Low)
Power
Ground
Power Ground
Logic
Output -
Open Drain
Status Flag
(Active Low)
Logic Input
Disable Input 1
(Active High)
Power
Output
H-Bridge Output 2
Analog
Output
Charge Pump
Capacitor
Source of high-side MOSFET1 and drain of low-side MOSFET1.
When D2 is logic LOW, both OUT1 and OUT2 are tri-stated. (Schmitt trigger
input with ~80 A sink so default condition = disabled.)
High-current power ground pins must be connected together physically as
close as possible and directly soldered down to a wide, thick, low resistance
ground plane on the PCB.
Open drain active LOW status flag output (requires an external pull-up resistor
to VDD. Maximum permissible load current < 0.5 mA. Maximum VCESAT
< 0.4 V at 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger
input with ~80 A source so default condition = disabled.
Source of high-side MOSFET2 and drain of low-side MOSFET2.
External reservoir capacitor connection for internal charge pump; connected to
VPWR. Allowable values are 30 to 100 F. Note: This capacitor is required for
the proper performance of the device.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33926
5
5 Page 
TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
5.0
0
VPWR
0
1.5 V
t DON
80%
1.5 V
TIME
Figure 4. Output Delay Time
t DOFF
20%
5.0 V
1.5 V
0V
tDDISABLE
90%
0V
TIME
Figure 5. Disable Delay Time
.
VPWR
tF
90%
tR
90%
10%
10%
0
TIME
Figure 6. Output Switching Time
Overload Condition
9.0 ISC Short-circuit Detection Threshold
6.5 Ilim
tB
tA
tB = Ilim Blanking Time
tA = Constant-OFF Time (OUT1 and OUT2 Tri-stated)
05..00
tON TIME
Figure 7. Current Limit Blanking Time and Constant-OFF Time
Analog Integrated Circuit Device Data
Freescale Semiconductor
33926
11
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