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Dual Gauge Driver Integrated Circuit

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Advance Information

Document Number: MC33970

Rev. 3.0, 1/2007

Dual Gauge Driver Integrated

Circuit with Improved Damping

Algorithms

33970

This 33970 is a single-packaged, Serial Peripheral Interface (SPI)

controlled, dual step motor gauge driver integrated circuit (IC). This

monolithic IC consists of four dual output H-Bridge coil drivers and the

associated control logic. Each pair of H-Bridge drivers is used to

automatically control the speed, direction, and magnitude of current

through the two coils of a two-phase instrumentation step motor,

similar to an MMT-licensed AFIC 6405.

The 33970 is ideal for use in automotive instrumentation systems

requiring distributed and flexible step motor gauge driving. The

device also eases the transition to step motors from air core motors

by emulating the air core pointer movement with little additional

processor bandwidth utilization.

IMPROVED GAUGE DRIVER

INTEGRATED CIRCUIT

DW SUFFIX

EG SUFFIX (Pb-FREE)

98ASB42344B

24-PIN SOICW

Features

• MMT-Licensed Two-Phase Step Motor Compatible

• Minimal Processor Overhead Required

• Fully Integrated Pointer Movement and Position State Machine

ORDERING INFORMATION

Device

Temperature

Range (TA)

Package

with Air Core Movement Emulation

• 4096 Possible Steady State Pointer Positions

• 340° Maximum Pointer Sweep

• Fixed Maximum Acceleration and Deceleration of 4500°/s2

MC33970DW/R2

MCZ33970EG/R2

-40°C to 125°C

24 SOICW

• Maximum Pointer Velocity of 400°/s

• Analog Microstepping (12 Steps/Degree of Pointer Movement)

• Pointer Calibration and Return to Zero

• SPI-Controlled 16-Bit Word

• Calibratable Internal Clock

• Low Sleep Mode Current

• Backward Compatible with MC33991

• Improved Pointer Movement, Diagnostics, and Return to Zero (RTZ)

• Pb-Free Packaging Designated by Suffix Code EG

VPWR

5.0 V

VDD

Regulator

33970

VPWR

VDD

SIN0+

SIN0-

COS0+

COS0-

Motor 0

MCU

RTZ SIN1+

RST SIN1-

SCLK

SI COS1+

COS1-

GND

Motor 1

Figure 1. 33970 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

Steady State

Input Pin Voltage (1)

SIN+/- COS+/- Continuous Per Output Current (2)

ESD Voltage (3)

Human Body Model

Machine Model

THERMAL RATINGS

VPWR(SUS)

VIN

IOUTMAX

VESD1

VESD2

-0.3 to 41

-0.3 to 7.0

±2000

±200

Storage Temperature

Operating Junction Temperature

Thermal Resistance

Junction to Ambient

Junction to Lead

THERMAL RESISTANCE

Peak Package Reflow Temperature During Reflow (4), (5)

TSTG

RθJA

RθJL

TPPRT

-55 to 150

-40 to 150

Note 5

°C

°C/W

°C

Notes

1. Exceeding voltage limits on Input pins may cause permanent damage to the device.

2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature

will require maximum output current computation using package thermal resistances.

3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

33970

Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TA < 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max Unit

POWER OUTPUT AND CLOCK TIMINGS

SIN, COS Output Turn ON Delay Time (Time from Rising CS Enabling

Outputs to Steady State Coil Voltages and Currents) (14)

tDLY (ON)

–

– 1.0

SIN, COS Output Turn OFF Delay Time (Time from Rising CS Disables

Outputs to Steady State Coil Voltages and Currents) (14)

tDLY (OFF)

–

– 1.0

Uncalibrated Oscillator Cycle Time

Calibrated Oscillator Cycle Time

Cal Pulse = 8.0 µs, PECCR D4 = Logic [0]

Cal pulse = 8.0 µs, PECCR D4 = Logic [1]

Maximum Pointer Speed (15)

Maximum Pointer Acceleration (15)

SPI INTERFACE TIMING (16)

tCLU

0.65

1.0

1.7

µs

tCLC

µs

1.0 1.1 1.2

0.9 1.0 1.1

VMAX

A MAX

–

– 400 °/s

–

4500

°/s2

Recommended Frequency of SPI Operation

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (17)

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (17)

SI to Falling Edge of SCLK (Required Setup Time) (17)

Required High State Duration of SCLK (Required Setup Time) (17)

Required Low State Duration of SCLK (Required Setup Time) (17)

Falling Edge of SCLK to SI (Required Hold Time) (17)

SO Rise Time

CL = 200 pF

fSPI

tLEAD

tLAG

tSISU

tWSCLKH

tWSCLKL

tSI (HOLD)

tRSO

–

1.0 3.0 MHz

50 167 ns

25 83 ns

– 167 ns

25 83 ns

25 50

SO Fall Time

CL = 200 pF

tFSO

– 25 50

SI, CS, SCLK, Incoming Signal Rise Time (18)

SI, CS, SCLK, Incoming Signal Fall Time (18)

Falling Edge of RST to Rising Edge of RST (Required Setup Time) (17)

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (17), (19)

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (17)

tRSI

tFSI

tWRST

t CS

tEN

–

– 50 ns

– 3.0 µs

– 5.0 µs

Notes

14. Maximum specified time for the 33970 is the minimum guaranteed time needed from the microcontroller.

15. The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally

calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.

16. The device shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the temperature

range specified. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall

be fully functional for slower clock speeds. See Figure 4 and 5.

17. The maximum setup time specified for the 33970 is the minimum time needed from the microcontroller to guarantee correct operation.

18. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

19. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes

Analog Integrated Circuit Device Data

Freescale Semiconductor

33970

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33970의 기능 및 특징 중 하나는 "Dual Gauge Driver Integrated Circuit" 입니다.

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