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PDF ATS75 Data sheet ( Hoja de datos )
| Número de pieza | ATS75 | |
| Descripción | LOW- OLTAGE 2-WIRE DIGITAL TEMPERATURE SENSOR | |
| Fabricantes | Andiglog | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ATS75 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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aTS75
LOW-VOLTAGE 2-WIRE DIGITAL TEMPERATURE SENSOR
With Thermal Alarm
Fully Released Specification
PRODUCT SPECIFICATION
Product Description
The aTS75 is a CMOS temperature sensor with a Delta-
Sigma temperature-to-digital converter and a SMBus
compatible serial digital interface. The aTS75 is accurate
to ±2° at 25°C and to ±3°C over the range of 0°C to 100°C.
The aTS75 provides digital temperature data with 9- to 12-
bit resolution. The default resolution is 9-bits, but for
applications requiring higher resolution, the user can
program the aTS75 to provide 10-, 11-, or 12-bit data.
The aTS75 features a thermal alarm function with a user-
programmable trip temperature and turn-off temperature.
This alarm can operate in two modes — interrupt mode and
comparator mode — which allows flexibility for many types
of applications.
The aTS75 is available in SOIC-8 and MSOP-8 surface
mount packages.
Pin Configuration
SOP8 and MSOP8
SDA
SCL
O.S.
18
27
aTS75
36
VDD
A0
A1
GND 4
5 A2
Features
User Configurable to 9-, 10-, 11-, or 12-bit Resolution
Calibrated to ±3°C from 0°C to 100°C
Temperature Range: -30°C to 125°C
Low Operating Current (less than 250μA)
Low Self Heating (0.2°C max in still air)
Operating Voltage Range: 2.7V to 5.5V
Applications
Battery Management
FAX Management
Printers
Portable Medical Instruments
HVAC
Power Supply Modules
Disk Drives
Computers
Automotive
Application Diagram
2.7V to 5.5V
8
User
Programmable
Address
A0 7
A1 6
aTS75
A2 5
8 Pin
3
Configuration
SMBus SDA 1
Interface SCL 2
O.S.
Ordering Information
Part Number
Package Temperature Range
aTS75D8
8-Lead SOIC
-30°C to 125°C
aTS75M8
8-Lead MSOP
-30°C to 125°C
AYWW – assembly site code, last digit of year, workweek
© Andigilog, Inc. 2005
-1-
www.andigilog.com
Marking
aTS75
AYWW
TS75
AYWW
How Supplied
2500 units Tape & Reel
2500 units Tape & Reel
April 2006 - 70A03204
1 page  
aTS75
Comparator Mode
In Comparator Mode, each time an temperature-to-
digital(T-to-D) temperature conversion occurs, the new
digital temperature is compared to the value stored in the
TOS and THYST Registers. If a fault tolerance number of
consecutive temperature measurements are greater than
the value stored in the TOS Register, the O.S. output will be
activated. For example, if bits F1 and F0 are equal to “10”
(fault tolerance = 4), four consecutive temperature
measurements must exceed TOS to activate the O.S.
output. Once the O.S output is active, it will remain active
until the first time the measured temperature drops below
the temperature stored in the THYST Register. The
operation of the alarm in Comparator Mode with fault
tolerance=2 is illustrated in Figure 1.
Temperature-to-Digital
Conversion
TOS
Interrupt Mode
In Interrupt Mode the O.S. output will first become active
after a fault tolerance number of consecutive temperature
measurements exceed the value stored in the TOS Register
(similar to Comparator Mode). Once O.S. is active, it can
only be cleared by a user read from any of the aTS75
registers (Temperature, Configuration, TOS, or THYST) or by
putting the aTS75 into Shutdown Mode (i.e., by setting the
shutdown bit in the Configuration Register to “1”). Once
cleared, the O.S. output can only be activated again by a
fault tolerance number of consecutive temperature
measurements that are lower than the value stored in
THYST. Again, once it is activated the O.S. output can only
be deactivated by a user read or shutdown. Thus, in
Interrupt Mode the activate/clear cycle for O.S. has the
following pattern:
temperature > TOS, clear,
temperature < THYST, clear, temperature > TOS, clear, etc.
The operation of the alarm in Interrupt Mode with fault
tolerance=2 is also illustrated in Figure 1.
THYST
O.S. (Comparator Mode)
O.S. (Interrupt Mode)
For this example:
Fault Tolerance = 2
Output Polarity = Active Low
Read (or Shutdown)
Figure 1. Thermal Alarm Operation in Comparator and Interrupt Modes
© Andigilog, Inc. 2005
-5-
www.andigilog.com
April 2006 - 70A03204
5 Page 
aTS75
Note: This segment of this timing diagram is a generic
pointer set cycle which must be followed by either an
immediate read cycle or write cycle as shown in this
figure and in figures 10, 11, and 12.
SCL . . . .
SDA
S 1 0 0 1 A2 A1 A0 R/W A 0 0 0 0 0 0 P1 P0 A
Address Byte
Ack
from
aTS75
Pointer Byte
Ack
from
aTS75
.SCL . .
SDA
S 1 0 0 1 A2 A1 A0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 0 0 0 0 N P
Repeat
Start
from
Address Byte
Ack
from
aTS75
Most Significant Data
Byte
(from aTS75)
Ack
from
Master
Least Significant Data Byte
(from aTS75)
No Ack
from
Master
Figure 8. Pointer set followed by immediate read from a 2-byte register (Temperature, TOS, or THYST Register)
SCL
SDA
S 1 0 0 1 A2 A1 A0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 0 0 0 0 N P
Address
Byte
Ack
from
aTS75
Most Significant Data
Byte
(from aTS75)
Ack
from
Master
Least Significant Data
Byte
(from aTS75)
No Ack
from
Master
Figure 9. Two-byte read from preset pointer location (Temperature, TOS, or THYST Register)
SCL
SDA
S1
00
1 A2 A1 A0 R/W A X D6 D5 D4 D3 D2 D1 D0 N P
Address Byte
Ack
from
aTS75
Data Byte
(from aTS75)
No Ack
from
Master
Figure 10 . One-byte read from Configuration Register with preset pointer
© Andigilog, Inc. 2005
- 11 -
www.andigilog.com
April 2006 - 70A03204
11 Page | ||
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