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XR16L2550 데이터시트 PDF




Exar Corporation에서 제조한 전자 부품 XR16L2550은 전자 산업 및 응용 분야에서
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부품번호 XR16L2550 기능
기능 LOW VOLTAGE DUART
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XR16L2550 데이터시트, 핀배열, 회로
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
SEPTEMBER 2010
REV. 1.1.3
GENERAL DESCRIPTION
The XR16L25501 (L2550) is a dual universal
asynchronous receiver and transmitter (UART). The
XR16L2550 is an improved version of the
ST16C2550 UART with lower operating voltages and
5 volt tolerant inputs. The L2550 provides enhanced
UART functions with 16 byte FIFOs, a modem control
interface and data rates up to 4 Mbps. Onboard
status registers provide the user with error indications
and operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates up to 3.125
Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
L2550 is available in a 44-pin PLCC, 48-pin TQFP
and 32-pin QFN packages. The L2550 is fabricated in
an advanced CMOS process.
NOTE: 1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
Portable Appliances
Medical Monitors
Base Stations
Micro Servers
Telecommunication Network Routers
Industrial Automation Controls
FIGURE 1. XR16L2550 BLOCK DIAGRAM
FEATURES
2.25 to 5.5 Volt operation
5 Volt tolerant inputs
Pin-to-pin compatible to Exar’s ST16C2450,
ST16C2550 and XR16L2750 in 44-PLCC and 48-
TQFP packages
Pin-to-pin compatible to XR16C2850 in 44-PLCC
Pin alike XR16L2551, XR16L2751 and
XR16C2850 in 48-TQFP package
Two independent UART channels
Up to 3.125Mbps with external clock of 50 MHz
Register Set compatible to 16C550
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable Receive FIFO interrupt trigger
levels
Automatic RTS/CTS hardware flow control
Automatic Xon/Xoff software flow control
Wireless infrared encoder/decoder
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
Tiny 32-QFN, no lead package (5x5x0.9mm)
44-PLCC and 48-TQFP packages also available
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
Reset
8-bit Data
Bus
Interface
* 5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 5.5 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XR16L2550 pdf, 반도체, 판매, 대치품
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
Pin Description
REV. 1.1.3
NAME
32-QFN 44-PLCC 48-TQFP
PIN #
PIN #
PIN #
TYPE
DESCRIPTION
TXRDYB#
-
12
6 O UART channel B Transmitter Ready (active low). The output pro-
vides the TX FIFO/THR status for transmit channel B. If it is not
used, leave it unconnected.
RXRDYB#
-
23 18 O UART channel B Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channel B. If it is not
used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA 5 13 7 O UART channel A Transmit Data. If it is not used, leave it uncon-
nected.
RXA 4 11 5 I UART channel A Receive Data. Normal receive data input must
idle at logic 1 condition. If it is not used, tie it to VCC or pull it high
via a 100k ohm resistor.
RTSA#
23
36
33 O UART channel A Request-to-Send (active low) or general pur-
pose output. This output must be asserted prior to using auto
RTS flow control, see EFR[6], MCR[1] and IER[6]. If it is not
used, leave it unconnected.
CTSA#
25
40
38
I UART channel A Clear-to-Send (active low) or general purpose
input. It can be used for auto CTS flow control, see EFR[7] and
IER[7]. This input should be connected to VCC when not used.
DTRA#
-
37 34 O UART channel A Data-Terminal-Ready (active low) or general
purpose output. If it is not used, leave it unconnected.
DSRA#
-
41 39 I UART channel A Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
CDA#
-
42 40 I UART channel A Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
RIA# - 43 41 I UART channel A Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
OP2A#
-
35 32 O Output Port 2 Channel A - The output state is defined by the user
and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to
a logic 1. INTA is set to the three state mode and OP2A# to a
logic 1 when MCR[3] is set to a logic 0. This output should not be
used as a general output else it will disturb the INTA output func-
tionality. If it is not used at all, leave it unconnected.
TXB 6 14 8 O UART channel B Transmit Data. If it is not used, leave it uncon-
nected.
RXB 3 10 4 I UART channel B Receive Data. Normal receive data input must
idle at logic 1 condition. If it is not used, tie it to VCC or pull it high
via a 100k ohm resistor.
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XR16L2550 전자부품, 판매, 대치품
XR16L2550
REV. 1.1.3
LOW VOLTAGE DUART WITH 16-BYTE FIFO
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2550 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3.
FIGURE 3. XR16L2550 DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
VCC
UART
Channel A
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
RIA#
OP2A#
CSA#
CSB#
INTA
INTB
UART
Channel B
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
TXB
RXB
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
RIB#
OP2B#
RESET
GND
VCC
RS-232 Serial Interface
RS-232 Serial Interface
.
2.2 5-Volt Tolerant Inputs
The L2550 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2550 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V.
2.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 13). An active high pulse of at least 40 ns duration will be required to activate the reset
function in the device.
2.4 Device Identification and Revision
The L2550 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is required to set the baud rate generator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2550
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
2.5 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
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관련 데이터시트

부품번호상세설명 및 기능제조사
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LOW VOLTAGE DUART

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