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XR16L2752 데이터시트 PDF




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부품번호 XR16L2752 기능
기능 2.25V TO 5.5V DUART
제조업체 Exar Corporation
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XR16L2752 데이터시트, 핀배열, 회로
xrwww.DataSheet4U.com
MAY 2005
GENERAL DESCRIPTION
The XR16L27521 (2752) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
operates from 2.25 to 5.5 Volt supply range and is
pin-to-pin compatible to Exar’s ST16C2552 and
XR16C2852. The 2752 register set is compatible to
the ST16C2552 and the XR16C2852 enhanced
features. It supports the Exar’s enhanced features of
64 bytes of TX and RX FIFOs, programmable FIFO
trigger level and FIFO level counters, automatic
hardware (RTS/CTS) and software flow control,
automatic RS-485 half duplex direction control output
and a complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Independent programmable
baud rate generators are provided in each channel to
select data rates up to 6.25 Mbps at 5 Volt and 8X
sampling. The 2752 is available in the 44-pin PLCC
package.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FIGURE 1. XR16L2752 BLOCK DIAGRAM
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
FEATURES
REV. 1.2.1
2.25 to 5.5 Volt Operation
5 Volt Tolerant Inputs
Pin-to-pin compatible to Exar’s ST16C2552 and
XR16C2852
Larger FIFO version of PC16C552
Two independent UART channels
Reg set compatible to 16C2552 and 16C2852
Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt
and 3 Mbps at 2.5 Volt with 8X sampling rate
Transmit and Receive FIFOs of 64 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Automatic RS-485 Half-duplex Direction
Control Output via RTS#
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
Alternate Function Register
Device Identification and Revision
Crystal oscillator or external clock input
Industrial and commercial temperature ranges
44-PLCC package
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
8-bit Data
Bus
Interface
*5 Volt Tolerant Inputs
(Except External Clock Input)
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Modem Control Logic
2.25 V to 5.5 V VCC
GND
TXA (or TXIRA)
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2752BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XR16L2752 pdf, 반도체, 판매, 대치품
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
xr
REV. 1.2.1
Pin Description
NAME
RXA
RTSA#
CTSA#
DTRA#
DSRA#
CDA#
RIA#
MFA#
44-PLCC
PIN #
39
36
40
37
41
42
43
35
TYPE
DESCRIPTION
I UART channel A Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin
is not used, tie it to VCC or pull it high via a 100k ohm resistor.
O UART channel A Request-to-Send (active low) or general purpose output. This output
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
I UART channel A Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
O UART channel A Data-Terminal-Ready (active low) or general purpose output. If this
pin is not used, leave it unconnected.
I UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I UART channel A Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
O Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD-
OUTA#, or RXRDYA# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 0 condition after a
reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers.
See Table 2 for more details.
TXB 26 O UART channel B Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
RXB
25 I UART channel B Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin
is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSB# 23 O UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
4

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XR16L2752 전자부품, 판매, 대치품
xr
REV. 1.2.1
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2752 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3
FIGURE 3. XR16L2750 DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IO R #
IO W #
UART_CS#
UART_CHSEL
U AR T_IN TA
U AR T_IN TB
TXRDYA#
(R X R D Y A # )
TXRDYB#
(R X R D Y B # )
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IO R #
IO W #
VCC
TXA
RXA
DTRA#
UART
Channel A
RTSA#
CTSA#
DSRA#
CDA#
R IA#
(O P2A#)
(BAUDO UTA#)
CS#
CHSEL
IN TA
IN TB
UART
Channel B
TXB
RXB
DTRB#
RTSB#
CTSB#
TXRDYA#
(R X R D Y A # )
TXRDYB#
(R X R D Y B # )
DSRB#
CDB#
R IB#
(O P2B#)
(BAUDO UTB#)
VCC
Serial Interface of
RS-232, RS-485
Serial Interface of
RS-232, RS-485
UART_RESET
RESET
GND
2 7 5 0 in t
P ins in parentheses becom e available through the M F # pin. M F # A /B becom es R X R D Y # A /B when AF R [2:1] = '10'. M F # A/B becom es O P 2# A /B
when A F R [2:1] = '00'. M F # A /B becom es B A U D O U T # A /B when AF R [1:0] = '01'.
2.2 5-Volt Tolerant Inputs
The 2752 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the 2752 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.
2.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.4 Device Identification and Revision
The XR16L2752 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the
XR16L2752 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
2.5 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
in Table 1.
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관련 데이터시트

부품번호상세설명 및 기능제조사
XR16L2750

2.25V TO 5.5V DUART

Exar Corporation
Exar Corporation
XR16L2751

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

Exar Corporation
Exar Corporation

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