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부품번호 XRT73L04B 기능
기능 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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XRT73L04B 데이터시트, 핀배열, 회로
www.DataSheet4U.com
XRT73L04B
OCTOBER 2003
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
GENERAL DESCRIPTION
The XRT73L04B, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit is a low power CMOS version of the
XRT73L04A and consists of four independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04B can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04B performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L04A
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
Low Power CMOS design
5V tolerant I/O
-40°C to +85°C Operating Temperature Range
Available in a Thermally Enhanced 144 pin LQFP
package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
FIGURE 1. XRT73L04B BLOCK DIAGRAM
E3_(n) STS-1/DS3_(n)
Host/(HW) RLOL_(n) EXClk_(n) RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
AGC/
Equalizer
Slicer
Clock
Recovery
Invert
REQEN_(n)
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
Peak
Detector
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
HDB3/
B3ZS
Decoder
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
MTIP_(n)
MRing_(n)
DMO_(n)
Device
Monitor
Tx
Control
Channel 0
Channel 1
Channel 2
Channel 3
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT73L04B pdf, 반도체, 판매, 대치품
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1.XRT73L04B Block Diagram ................................................................................................................ 1
TYPICAL APPLICATIONS ................................................................................................................................. 2
Figure 2.MultiChannel ATM Application ............................................................................................................ 2
Figure 3.MultiService - Frame Relay Application .............................................................................................. 2
TRANSMIT INTERFACE CHARACTERISTICS: ..................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS: ....................................................................................................... 2
Figure 4.Pin out of the XRT73L04B in the 144 Pin TQFP package .................................................................. 3
ORDERING INFORMATION ....................................................................................................... 3
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS (BY FUNCTION) ......................................................................................... 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ........................................................................................................................................ 7
OPERATING MODE SELECT ........................................................................................................................... 8
CONTROL AND ALARM INTERFACE ................................................................................................................. 9
MICROPROCESSOR INTERFACE .................................................................................................................... 11
POWER AND GROUND PINS ......................................................................................................................... 13
NO CONNECTION PINS ................................................................................................................................ 14
ELECTRICAL CHARACTERISTICS ........................................................................................... 15
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15
DC Electrical Characteristics .......................................................................................................... 15
AC Electrical Characteristics (See Figure 5) ........................................................................................................ 16
Terminal Side Timing Parameters (See Figure 6 and Figure 7) -- {(n) = 0, 1, 2 or 3 } ......................................... 16
Figure 5.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel) .................. 17
Figure 6.Timing Diagram of the Transmit Terminal Input Interface ................................................................. 17
Figure 7.Timing Diagram of the Receive Terminal Output Interface ............................................................... 17
Line Side Parameters E3 Application ................................................................................................................... 18
Transmit Characteristics (see Figure 5) ............................................................................................................... 18
Line Side Parameters Sonet STS-1 Application ................................................................................................... 19
Transmit Characteristics (See Figure 5) ............................................................................................................... 19
Line Side Parameters DS3 Application ................................................................................................................ 20
Transmit Characteristics (see Figure 5) ............................................................................................................... 20
Figure 8.ITU-T G.703 Transmit Output Pulse Template for E3 Applications .................................................. 21
Figure 9.Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ............................. 21
Figure 10.Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ........... 22
Figure 11.Microprocessor Serial Interface Data Structure .............................................................................. 22
Microprocessor Serial Interface Timing (See Figure 12) ...................................................................................... 23
Figure 12.Timing Diagram for the Microprocessor Serial Interface ................................................................. 23
SYSTEM DESCRIPTION .................................................................................................. 24
THE TRANSMIT SECTION - CHANNELS 0, 1, 2, AND 3 .................................................................................... 24
THE RECEIVE SECTION - CHANNELS 0, 1, 2 AND 3 ....................................................................................... 24
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................. 24
Table 1:Role of Microprocessor Serial Interface pins when the XRT73L04B is operating in the Hardware Mode
24
Figure 13.Functional Block Diagram of the XRT73L04B ................................................................................ 25
I

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XRT73L04B 전자부품, 판매, 대치품
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
COMMAND REGISTER CR4-(N) ............................................................................................................ 48
Figure 34.The Digital Local Loop-Back path within a given channel .............................................................. 48
COMMAND REGISTER CR4-(N) ............................................................................................................ 48
4.3 THE REMOTE LOOP-BACK MODE ................................................................................................... 49
Figure 35.The Remote Loop-Back path, within a given channel .................................................................... 49
COMMAND REGISTER CR4-(n) ............................................................................................................ 49
4.4 TXOFF FEATURES ......................................................................................................................... 50
COMMAND REGISTER CR1-(N) ............................................................................................................ 50
Table 6:The Relationship Between the TxOFF Input Pin, the TxOFF Bit Field and the State of the Transmitter
50
4.5 THE TRANSMIT DRIVE MONITOR FEATURES .................................................................................... 50
Figure 36.The XRT73L04B employing the Transmit Drive Monitor Features ................................................. 51
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ................................................................................. 51
5.0 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 51
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................. 51
COMMAND REGISTER CR1-(N) ............................................................................................................ 51
Table 7:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ............................... 52
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ......................................................... 53
Command Register - CR0-(n) ............................................................................................................ 53
COMMAND REGISTER CR0-(N) ............................................................................................................. 53
COMMAND REGISTER CR1-(N) ............................................................................................................ 54
Command Register CR2-(n) .............................................................................................................. 54
COMMAND REGISTER CR2-(N) ............................................................................................................ 54
COMMAND REGISTER CR3-(N) ............................................................................................................ 55
COMMAND REGISTER CR4-(N) ............................................................................................................ 56
Table 8:Contents of LLB_(n) and RLB_(n) and the Corresponding Loop-Back Mode for Channel(n) ........... 56
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................. 56
Figure 37.Microprocessor Serial Interface Data Structure ............................................................................. 57
Figure 38.Timing Diagram for the Microprocessor Serial Interface ................................................................ 58
ORDERING INFORMATION ..................................................................................................... 59
PACKAGE DIMENSIONS ........................................................................................................ 59
REVISION HISTORY ..................................................................................................................................... 60
IV

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관련 데이터시트

부품번호상세설명 및 기능제조사
XRT73L04A

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation
XRT73L04B

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation

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