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부품번호 XRT73LC03A 기능
기능 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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XRT73LC03A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
XRT73LC03A
OCTOBER 2003
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
GENERAL DESCRIPTION
The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line
Interface Unit is a low power CMOS version of the
XRT73L03A and consists of three independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73LC03A can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73LC03A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L03A
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
Low power CMOS design
5V tolerant I/O
-40°C to +85°C Operating Temperature Range
Available in a 120 pin LQFP package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
FIGURE 1. XRT73LC03A BLOCK DIAGRAM
E3_(n)
STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
REQEN_(n)
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
TTIP_(n)
TRing_(n)
MTIP_(n)
MRing_(n)
DMO_(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
Device
Monitor
Pulse
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Channel 2 - (n) = 2
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT73LC03A pdf, 반도체, 판매, 대치품
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
TYPICAL APPLICATIONS ................................................................................................................................. 2
TRANSMIT INTERFACE CHARACTERISTICS: ..................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS: ....................................................................................................... 2
ORDERING INFORMATION ............................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ........................................................................................................................................ 7
OPERATING MODE SELECT ........................................................................................................................... 7
CONTROL AND ALARM INTERFACE ................................................................................................................. 9
MICROPROCESSOR INTERFACE .................................................................................................................... 11
POWER AND GROUND PINS ......................................................................................................................... 13
NO CONNECTION PINS ................................................................................................................................ 14
ELECTRICAL CHARACTERISTICS ................................................................................ 15
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15
SYSTEM DESCRIPTION .................................................................................................. 24
THE TRANSMIT SECTION - CHANNELS 0, 1 AND 2 ......................................................................................... 24
THE RECEIVE SECTION - CHANNELS 0, 1 AND 2 ........................................................................................... 24
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................. 24
1.0 Selecting the Data Rate .................................................................................................................... 25
1.1 CONFIGURING CHANNEL(N) ............................................................................................................................... 25
2.0 The Transmit Section ....................................................................................................................... 27
COMMAND REGISTER, CR4-(N) ...................................................................................................... 27
2.1 THE TRANSMIT LOGIC BLOCK ............................................................................................................................ 27
2.1.1 Accepting Dual-Rail Data from the Terminal Equipment ...................................................................... 27
2.1.2 Accepting Single-Rail Data from the Terminal Equipment ................................................................... 28
COMMAND REGISTER CR1-(N) ....................................................................................................... 28
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................................... 29
2.3 THE HDB3/B3ZS ENCODER BLOCK .................................................................................................................. 29
2.3.1 B3ZS Encoding .................................................................................................................................... 29
2.3.2 HDB3 Encoding .................................................................................................................................... 30
2.3.3 Disabling the HDB3/B3ZS Encoder ..................................................................................................... 30
COMMAND REGISTER CR2-(N) ....................................................................................................... 30
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY ....................................................................................................... 31
2.4.1 Enabling the Transmit Line Build-Out Circuit ....................................................................................... 32
COMMAND REGISTER, CR1-(N) ...................................................................................................... 32
2.4.2 Disabling the Transmit Line Build-Out Circuit ....................................................................................... 32
COMMAND REGISTER, CR1-(N) ...................................................................................................... 33
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit ......................................................... 33
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications .................................................................... 33
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73LC03A TO THE LINE ...................................................... 33
TRANSFORMER RECOMMENDATIONS ............................................................................................... 34
3.0 The Receive Section ......................................................................................................................... 35
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73LC03A TO THE LINE ........................................................ 35
3.2 THE RECEIVE EQUALIZER BLOCK ...................................................................................................................... 36
3.2.1 Guidelines for Setting the Receive Equalizer ...................................................................................... 36
COMMAND REGISTER CR2-(N) ....................................................................................................... 37
3.3 CLOCK RECOVERY PLL .................................................................................................................................... 38
3.3.1 The Training Mode ............................................................................................................................... 38
3.3.2 The Data/Clock Recovery Mode .......................................................................................................... 38
I

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XRT73LC03A 전자부품, 판매, 대치품
TRANSMIT INTERFACE
PIN #
NAME
35 TxLEV_0
8 TxLEV_1
9 TxLEV_2
117 TxOFF_0
116 TxOFF_1
115 TxOFF_2
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
TYPE
I
I
DESCRIPTION
Transmit Line Build-Out Enable/Disable Select - Channel (n):
This input pin permits the Transmit Line Build-Out circuit within Channel
(n) to be enabled or disabled. In E3 mode, this pin has no effect on the
transmit pulse shape.
Setting this pin to "High" disables the Line Build-Out circuit. In this
mode, Channel (n) outputs partially-shaped pulses onto the line via the
TTIP_(n) and TRing_(n) output pins.
Setting this pin to "Low" enables the Line Build-Out circuit within Chan-
nel (n). In this mode, Channel (n) outputs shaped pulses onto the line
via the TTIP_(n) and TRing_(n) output pins.
To comply with the Isolated DSX-3/STSX-1 Pulse Template Require-
ments per Bellcore GR-499-CORE or Bellcore GR-253-CORE:
a. Set this input pin to "1" if the cable length between the Cross-
Connect and the transmit output of Channel (n) is greater than
225 feet.
b. Set this input pin to "0" if the cable length between the Cross-
Connect and the transmit output of Channel (n) is less than 225
feet.
This pin is active only if the following two conditions are true:
a. The XRT73LC03A is configured to operate in either the DS3 or
SONET STS-1 Modes.
b. The XRT73LC03A is configured to operate in the Hardware
Mode.
NOTE: This pin to should be tied to GND if the XRT73LC03A is going to
be operating in the HOST Mode, (internally pulled-down).
Transmitter OFF Input - Channel (n):
Setting this input pin "High" turns off all of the Transmitter Sections. In
this mode the TTIP and TRing outputs are tri-stated.
NOTES:
1. This input pin controls the TTIP and TRing outputs even when
the XRT73LC03A is operating in the HOST Mode.
2. For HOST Mode Operation, this pin is tied to GND if the Trans-
mitter is intended to be turned off via the Microprocessor Serial
Interface.
5

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부품번호상세설명 및 기능제조사
XRT73LC03A

3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation

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