|
|
PDF XRT73R06 Data sheet ( Hoja de datos )
| Número de pieza | XRT73R06 | |
| Descripción | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XRT73R06 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
áçwww.DataSheet4U.com
XRT73R06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
DECEMBER 2004
GENERAL DESCRIPTION
The XRT73R06 is a six channel fully integrated Line
Interface Unit (LIU) featuring EXAR’s R3 Technology
(Reconfigurable, Relayless, Redundancy) for E3/
DS3/STS-1 applications. The LIU incorporates 6
independent Receivers, Transmitters and Jitter
Attenuators in a single 217 Lead BGA package.
Each channel of the XRT73R06 can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT73R06’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
REV. 1.0.0
The XRT73R06 provides a Parallel Microprocessor
Interface for programming and control.
The XRT73R06 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
• E3/DS3 Access Equipment
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73R06
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
RTIP_n
RRing_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
µProcessor Interface
XRT73R06
XRT73R06
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
MUX
Remote
LoopBack
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
HDB3/
MUX B3ZS
Encoder
Channel 0
Channel n...
Channel 5
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TxON
PART NUMBER
XRT73R06IB
ORDERING INFORMATION
PACKAGE
217 Lead BGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
áç
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73R06
REV. 1.0.0
Figure 18. Receive Path Block Diagram ......................................................................................................... 30
4.1 RECEIVE LINE INTERFACE ................................................................................................................................ 30
Figure 19. Receive Line InterfaceConnection ................................................................................................ 30
4.2 ADAPTIVE GAIN CONTROL (AGC) .................................................................................................................... 31
4.3 RECEIVE EQUALIZER ........................................................................................................................................ 31
Figure 20. ACG/Equalizer Block Diagram ...................................................................................................... 31
4.3.1 Recommendations for Equalizer Settings ....................................................................................... 31
4.4 CLOCK AND DATA RECOVERY .......................................................................................................................... 31
4.4.1 Data/Clock Recovery Mode ............................................................................................................... 31
4.4.2 Training Mode .................................................................................................................................... 31
4.5 LOS (LOSS OF SIGNAL) DETECTOR .................................................................................................................. 32
4.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 32
4.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 32
TABLE 6: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 32
4.5.3 E3 LOS Condition: ............................................................................................................................. 33
Figure 21. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 33
Figure 22. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 33
4.5.4 Interference Tolerance ...................................................................................................................... 34
Figure 23. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 34
Figure 24. Interference Margin Test Set up for E3. ........................................................................................ 34
TABLE 7: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 35
4.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 36
4.6 B3ZS/HDB3 DECODER ................................................................................................................................... 36
Figure 25. Receiver Data output and code violation timing ............................................................................ 36
5.0 Jitter .................................................................................................................................................. 37
5.1 JITTER TOLERANCE .......................................................................................................................................... 37
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 37
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 37
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 38
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 38
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 38
5.2 JITTER TRANSFER ............................................................................................................................................ 39
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ....................................... 39
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................. 39
TABLE 10: JITTER TRANSFER PASS MASKS ....................................................................................................... 39
5.2.1 Jitter Generation ................................................................................................................................ 40
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 40
6.0 Diagnostic Features ......................................................................................................................... 41
6.1 PRBS GENERATOR AND DETECTOR ................................................................................................................. 41
Figure 30. PRBS MODE ................................................................................................................................. 41
6.2 LOOPBACKS ................................................................................................................................................ 42
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 42
Figure 31. Analog Loopback ........................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 43
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 43
Figure 32. Digital Loopback ............................................................................................................................ 43
Figure 33. Remote Loopback ......................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 44
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 44
7.0 Microprocessor interface Block ..................................................................................................... 46
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ...................................................................... 46
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 46
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ........................................................................................ 47
TABLE 12: XRT73R06 MICROPROCESSOR INTERFACE SIGNALS ........................................................................ 47
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION ......................................................................................... 48
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ......................................................................................... 49
2
5 Page 
áç
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73R06
REV. 1.0.0
CLOCK INTERFACE
LEAD # SIGNAL NAME TYPE
DESCRIPTION
E15 E3CLK I E3 Clock Input (34.368 MHz ± 20 ppm):
If any of the channels is configured in E3 mode, a reference clock 34.368 MHz
is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
G16 DS3CLK I DS3 Clock Input (44.736 MHz ± 20 ppm):
If any of the channels is configured in DS3 mode, a reference clock 44.736
MHz. is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
C16 STS-1CLK/ I STS-1 Clock Input (51.84 MHz ± 20 ppm):
12M If any of the channels is configured in STS-1 mode, a reference clock 51.84
MHz is applied on this pin..
In Single Frequency Mode, a reference clock of 12.288 MHz ± 20 ppm is con-
nected to this pin and the internal clock synthesizer generates the appropriate
clock frequencies based on the configuration of the channels in E3, DS3 or
STS-1 modes.
L15 SFM_EN I Single Frequency Mode Enable:
Tie this pin “High” to enable the Single Frequency Mode. A reference clock of
12.288 MHz ± 20 ppm is applied.
In the Single Frequency Mode (SFM) a low jitter output clock is provided for
each channel if the CLK_EN bit is set thus eliminating the need for a separate
clock source for the framer.
Tie this pin “Low” if single frequency mode is not selected. In this case, the
appropriate reference clocks must be provided.
NOTE: This pin is internally pulled down
B1 CLKOUT_0 O Clock output for channel 0
T1 CLKOUT_1
B17 CLKOUT_2
T17 CLKOUT_3
D11 CLKOUT_4
P11 CLKOUT_5
Clock output for channel 1
Clock output for channel 2
Clock output for channel 3
Clock output for channel 4
Clock output for channel 5
Low jitter clock output for each channel based on the mode selection (E3,DS3
or STS-1) if the CLKOUTEN_n bit is set in the control register.
This eliminates the need for a separate clock source for the framer.
NOTES:
1. The maximum drive capability for the clockouts is 16 mA.
2. This clock out is available both in SFM and non-SFM modes.
8
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT73R06.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XRT73R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | Exar Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |