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XRT75L00D 데이터시트 PDF




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부품번호 XRT75L00D 기능
기능 E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT75L00D 데이터시트, 핀배열, 회로
www.DataSheet4U.com
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FEBRUARY 2004
GENERAL DESCRIPTION
The XRT75L00D is a single-channel fully integrated
Line Interface Unit (LIU) with Sonet Desynchronizer
for E3/DS3/STS-1 applications. It incorporates an
independent Receiver, Transmitter and Jitter
Attenuator in a single 52 pin TQFP package.
The XRT75L00D can be configured to operate in
either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes. The transmitter can be turned
off (tri-stated) for redundancy support and for
conserving power.
The XRT75L00D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L00D incorporates an advanced crystal-
less jitter attenuator that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications. Also, the jitter attenuator can
be used for clock smoothing in SONET STS-1 to DS3
de-mapping.
The XRT75L00D provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L00D supports local, remote and digital
loop-backs. The XRT75L00D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets E3/DS3/STS-1
Requirements.
Jitter
Tolerance
Detects and Clears LOS as per G.775.
Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards.
Meets ETSI TBR 24 Jitter Transfer Requirements.
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
REV. 1.0.2
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
Provides low jitter output clock.
TRANSMITTER:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitter can be turned on or off.
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator.
Jitter Attenuator can be selected in Receive or
Transmit paths.
16, 32 or 128 bits selectable FIFO size.
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
Jitter Attenuator can be disabled.
De-Synchronizer for SONET STS-1 to DS-3
demapping.
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration.
Supports optional internal Transmit Driver
Monitoring.
PRBS error counter register to accumulate errors.
Hardware Mode for control and configuration.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V ± 5% power supply.
5 V Tolerant I/O.
Available in 52 pin TQFP.
-40°C to 85°C Industrial Temperature Range.
APPLICATIONS
E3/DS3 Access Equipment.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT75L00D pdf, 반도체, 판매, 대치품
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
PART NUMBER
XRT75L00DIV
ORDERING INFORMATION
PACKAGE
52 Pin TQFP
OPERATING TEMPERATURE RANGE
-40°C to +85°C
4

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XRT75L00D 전자부품, 판매, 대치품
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L00D
REV. 1.0.2
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .............................. 57
9.2.2.2 THE 44.736MBPS + 1PPM CASE ........................................................................................................................... 58
FIGURE 39. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3
SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL................................................................ 58
9.2.2.3 THE 44.736MBPS - 1PPM CASE ............................................................................................................................ 59
9.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS .............................................................................. 60
9.3.1 THE CONCEPT OF AN STS-1 SPE POINTER........................................................................................................... 60
FIGURE 40. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL
THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL ............................................................................ 60
FIGURE 41. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES .................................... 61
9.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK .................................................................................. 62
FIGURE 42. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION
OF THE J1 BYTE, DESIGNATED......................................................................................................................................... 62
FIGURE 43. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2
BYTES) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME ................................ 62
9.3.3 CAUSES OF POINTER ADJUSTMENTS ................................................................................................................... 63
FIGURE 44. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER ............................................................. 64
FIGURE 45. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS
DESIGNATED................................................................................................................................................................... 65
FIGURE 46. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS
DESIGNATED................................................................................................................................................................... 66
9.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ............................................................................... 67
9.4 CLOCK GAPPING JITTER ............................................................................................................................. 67
FIGURE 47. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION.................................. 67
9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
FOR DS3 APPLICATIONS ............................................................................................................................ 68
TABLE 18: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS.. 68
9.5.1 DS3 DE-MAPPING JITTER......................................................................................................................................... 69
9.5.2 SINGLE POINTER ADJUSTMENT ............................................................................................................................. 69
9.5.3 POINTER BURST........................................................................................................................................................ 69
FIGURE 48. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO ......................................................................................... 69
9.5.4 PHASE TRANSIENTS................................................................................................................................................. 70
FIGURE 49. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO..................................................................................... 70
FIGURE 50. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO ..................................................................... 70
9.5.5 87-3 PATTERN............................................................................................................................................................ 71
9.5.6 87-3 ADD ..................................................................................................................................................................... 71
FIGURE 51. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN ............................................................. 71
9.5.7 87-3 CANCEL.............................................................................................................................................................. 72
FIGURE 52. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN ................................................................................ 72
FIGURE 53. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO................................................................................ 72
9.5.8 CONTINUOUS PATTERN........................................................................................................................................... 73
9.5.9 CONTINUOUS ADD ................................................................................................................................................... 73
FIGURE 54. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO................................................................ 73
9.5.10 CONTINUOUS CANCEL........................................................................................................................................... 74
FIGURE 55. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO ........................................................................ 74
FIGURE 56. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO................................................................... 74
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ................................. 75
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION ............................................................................................................................................... 75
9.7.1 INTRINSIC JITTER TEST RESULTS.......................................................................................................................... 75
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS..................................... 75
9.7.2 WANDER MEASUREMENT TEST RESULTS............................................................................................................ 76
9.8 DESIGNING WITH THE LIU ........................................................................................................................... 76
9.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRIN-
SIC JITTER AND WANDER REQUIREMENTS ............................................................................................................ 76
FIGURE 57. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS.......................... 76
CHANNEL CONTROL REGISTER..................................................................................................................... 77
CHANNEL CONTROL REGISTER..................................................................................................................... 78
JITTER ATTENUATOR CONTROL REGISTER.................................................................................................... 78
9.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR
TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ........................ 79
9.8.2.1 SOME NOTES PRIOR TO STARTING THIS DISCUSSION: ............................................................................ 79
JITTER ATTENUATOR CONTROL REGISTER.................................................................................................... 79
JITTER ATTENUATOR CONTROL REGISTER.................................................................................................... 79
9.8.2.2 OUR PRE-PROCESSING RECOMMENDATIONS ............................................................................................ 80
3

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관련 데이터시트

부품번호상세설명 및 기능제조사
XRT75L00

E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation
XRT75L00D

E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation

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