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부품번호 XRT75L03D 기능
기능 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT75L03D 데이터시트, 핀배열, 회로
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
JUNE 2003
GENERAL DESCRIPTION
The XRT75L03D is a three-channel fully integrated
Line Interface Unit (LIU) with Jitter Attenuator for E3/
DS3/STS-1 applications. It incorporates 3
independent Receivers, Transmitters and Jitter
Attenuators in a single 128 pin LQFP package.
Each channel of the XRT75L03D can be
independently configured to operate in the data rate,
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz). Each transmitter can be turned off and tri-
stated for redundancy support or for conserving
power.
The XRT75L03D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L03D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75L03D provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L03D supports local, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
FEATURES
TRANSMITTER:
REV. 1.0.0
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Each Transmitter can be turned on or off
Transmitters provide Current Drive Output
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator for
each channel
Jitter Attenuator can be selected in Receive or
Transmit paths
Meets ETSI TBR 24 Jitter Transfer Requirements
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
Jitter Attenuator can be disabled
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration
Supports optional internal Transmit driver
monitoring
Hardware Mode for control and configuration
Each channel supports Local, Remote and Digital
Loop-backs
Single 3.3 V ± 5% power supply
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance
Meets E3/DS3/STS-1 Jitter Tolerance Requirement
Detects and Clears LOS as per G.775
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
Provides low jitter output clock
5 V Tolerant I/O
Available in 128 pin Thermally enhanced LQFP
Package
- 40°C to 85°C Industrial Temperature Range
APPLICATIONS
E3/DS3 Access Equipment
STS1-SPE to DS3 De-Synchronizing
DSLAMs
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT75L03D pdf, 반도체, 판매, 대치품
XRT75L03D
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REV. 1.0.0 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
GENERAL DESCRIPTION ............................................................................................... 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2
Figure 1. Block Diagram of the XRT 75L03D .................................................................................................... 2
Figure 2. Pin Out of the XRT75L03D ................................................................................................................ 3
ORDERING INFORMATION ................................................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS ...................................................................... 4
TRANSMIT LINE SIDE PINS ............................................................................................................................ 8
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS .................................................................... 10
RECEIVE LINE SIDE PINS ............................................................................................................................ 17
CLOCK INTERFACE ...................................................................................................................................... 18
GENERAL CONTROL PINS ........................................................................................................................... 19
CONTROL AND ALARM INTERFACE ............................................................................................................... 21
JITTER ATTENUATOR INTERFACE ................................................................................................................. 21
POWER SUPPLY AND GROUND PINS ............................................................................................................ 24
XRT75L03D PIN LISTING IN NUMERICAL ORDER ......................................................................................... 26
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 31
TABLE 1: ABSOLUTE MAXIMUM RATINGS ............................................................................................................ 31
TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................... 31
2.0 TIMING CHARACTERISTICS ............................................................................................................ 32
Figure 3. Typical interface between terminal equipment and the XRT75L03D (dual-rail data) ....................... 32
Figure 4. Transmitter Terminal Input Timing ................................................................................................... 32
Figure 5. Receiver Data output and code violation timing .............................................................................. 33
Figure 6. Transmit Pulse Amplitude test circuit for E3, DS3 and STS-1 Rates ............................................... 33
3.0 LINE SIDE CHARACTERISTICS: ..................................................................................................... 34
3.1 E3 LINE SIDE PARAMETERS: ............................................................................................................................. 34
Figure 7. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ..................................................... 34
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ........................... 35
Figure 8. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ............ 36
TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 36
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . 37
Figure 9. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 .................................................. 38
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 38
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ..... 39
Figure 10. Microprocessor Serial Interface Structure ...................................................................................... 39
Figure 11. Timing Diagram for the Microprocessor Serial Interface ................................................................ 40
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) ..... 40
FUNCTIONAL DESCRIPTION: ........................................................................................ 41
4.0 The Transmitter Section: ................................................................................................................. 41
Figure 12. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 41
Figure 13. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 41
4.1 TRANSMIT CLOCK: ........................................................................................................................................... 42
4.2 B3ZS/HDB3 ENCODER: .................................................................................................................................. 42
4.2.1 B3ZS Encoding: ................................................................................................................................. 42
4.2.2 HDB3 Encoding: ................................................................................................................................. 42
Figure 14. B3ZS Encoding Format ................................................................................................................. 42
Figure 15. HDB3 Encoding Format ................................................................................................................. 42
4.3 TRANSMIT PULSE SHAPER: .............................................................................................................................. 43
4.3.1 Guidelines for using Transmit Build Out Circuit: ............................................................................ 43
4.3.2 Interfacing to the line: ........................................................................................................................ 43
4.4 TRANSMIT DRIVE MONITOR: ............................................................................................................................. 44
4.5 TRANSMITTER SECTION ON/OFF: ...................................................................................................................... 44
5.0 The Receiver Section: ...................................................................................................................... 44
I

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XRT75L03D 전자부품, 판매, 대치품
áç
XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 AP-
PLICATIONS ........................................................................................................................................................................ 110
TABLE 31: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS .................................................................................................................................. 110
9.5.1 DS3 De-Mapping Jitter ..................................................................................................................... 111
9.5.2 Single Pointer Adjustment .............................................................................................................. 111
Figure 48. Illustration of Single Pointer Adjustment Scenario ...................................................................... 111
9.5.3 Pointer Burst .................................................................................................................................... 112
9.5.4 Phase Transients ............................................................................................................................. 112
Figure 49. Illustration of Burst of Pointer Adjustment Scenario .................................................................... 112
Figure 50. Illustration of "Phase-Transient" Pointer Adjustment Scenario ................................................... 112
9.5.5 87-3 Pattern ...................................................................................................................................... 113
9.5.6 87-3 Add ............................................................................................................................................ 113
Figure 51. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ............................................. 113
9.5.7 87-3 Cancel ....................................................................................................................................... 114
Figure 52. Illustration of the 87-3 Add Pointer Adjustment Pattern .............................................................. 114
Figure 53. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................. 114
9.5.8 Continuous Pattern .......................................................................................................................... 115
9.5.9 Continuous Add .............................................................................................................................. 115
Figure 54. Illustration of Continuous Periodic Pointer Adjustment Scenario ............................................... 115
9.5.10 Continuous Cancel ........................................................................................................................ 116
Figure 55. Illustration of Continuous-Add Pointer Adjustment Scenario ....................................................... 116
Figure 56. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................. 116
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................................. 117
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE XRT75L03D IN A TYPICAL SYSTEM APPLI-
CATION ............................................................................................................................................................................ 117
9.7.1 Intrinsic Jitter Test results .............................................................................................................. 117
TABLE 32: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ..... 117
9.7.2 Wander Measurement Test Results ............................................................................................... 118
9.8 DESIGNING WITH THE XRT75L03D ................................................................................................................. 118
9.8.1 How to design and configure the XRT75L03D to permit a system to meet the above-mentioned
Intrinsic Jitter and Wander requirements ..................................................................................................................... 118
Figure 57. Illustration of the XRT75L03D being connected to a Mapper IC for SONET De-Sync Applications ..
118
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 119
CHANNEL 1 ADDRESS LOCATION = 0X0E ......................................... 119
CHANNEL 2 ADDRESS LOCATION = 0X16 ......................................... 119
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 120
CHANNEL 1 ADDRESS LOCATION = 0X0E .............................................. 120
CHANNEL 2 ADDRESS LOCATION = 0X16 ............................................... 120
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ............................... 120
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................. 120
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................. 120
9.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to
routing this DS3 Clock and Data-Signals to the Transmit Inputs of the XRT75L03D .............................................. 121
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ 121
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................ 121
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................ 121
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ 121
CHANNEL 1 ADDRESS LOCATION = 0X0F ........................... 121
CHANNEL 2 ADDRESS LOCATION = 0X17 ........................... 121
Figure 58. Illustration of MINOR PATTERN P1 ............................................................................................ 122
Figure 59. Illustration of MINOR PATTERN P2 ............................................................................................ 123
Figure 60. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A .............................. 123
Figure 61. Illustration of MINOR PATTERN P3 ............................................................................................ 124
Figure 62. Illustration of Procedure which is used to Synthesize PATTERN B ........................................... 124
Figure 63. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC ............ 125
IV

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관련 데이터시트

부품번호상세설명 및 기능제조사
XRT75L03

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation
XRT75L03D

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation

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