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PDF XRT75L04 Data sheet ( Hoja de datos )
| Número de pieza | XRT75L04 | |
| Descripción | FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
JULY 2006
REV. 1.0.4
GENERAL DESCRIPTION
The XRT75L04 is a four-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates four independent
Receivers, Transmitters and Jitter Attenuators in a
single 176 pin LQFP package.
Each channel of the XRT75L04 can be configured to
operate in E3 (34.368 MHz), DS3 (44.736 MHz) or
STS-1 (51.84 MHz) rates that are independent of
each other. Each transmitter can be turned off and tri-
stated for redundancy support and for conserving
power.
The XRT75L04’s differential receivers provide high
noise interference margin and are able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L04 incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Telcordia GR-499, GR-253 specifications.
The XRT75L04 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L04 supports local, remote and digital
loop-backs. The XRT75L04 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance.
• Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
• On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
• On-chip clock synthesizer generates the
appropriate rate clock from a single frequency
XTAL.
• Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
TRANSMITTER:
• Compliant with Telcordia GR-499, GR-253 and
ANSI T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Transmitters can be turned on or off.
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator.
• Jitter Attenuators can be selected in Receive or
Transmit paths.
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-253 and GR-499-
CORE,1995 standards.
• Meets ETSI TBR 24 Jitter Transfer Requirements.
• 16 or 32 bits selectable FIFO size.
• Meets the Wander specifications described in
T1.105.03b.
• Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
• Serial Microprocessor Interface for control and
configuration.
• Supports optional internal Transmit Driver
Monitoring.
• PRBS error counter register to accumulate errors.
• Supports Local, Remote and Digital Loop-backs.
• Single 3.3 V ± 5% power supply.
• 5 V Tolerant I/O.
• Maximum Power Dissipation 1.5W.
• Available in 176 pin LQFP package
• - 40°C to 85°C Industrial Temperature Range.
APPLICATIONS
• E3/DS3 Access Equipment.
• STS1-SPE to DS3 Mapper.
• DSLAMs.
• Digital Cross Connect Systems.
• CSU/DSU Equipment.
• Routers.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 31
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3. ............................................................................................................ 32
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 32
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 32
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 32
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 33
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 33
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-
1 APPLICATIONS) ............................................................................................................................................................ 33
DISABLING ALOS/DLOS DETECTION: .......................................................................................................... 33
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 33
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.......................................................................................... 34
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 34
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 35
6.0 JITTER: ................................................................................................................................................ 36
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 36
FIGURE 21. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 36
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 36
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 37
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 37
FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 37
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................. 38
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 38
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................................................ 38
6.3 JITTER GENERATION: .................................................................................................................................. 38
6.4 JITTER ATTENUATOR: ................................................................................................................................. 38
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 39
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 39
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 40
TABLE 14: FUNCTIONS OF SHARED PINS ......................................................................................................................................... 40
TABLE 15: REGISTER MAP AND BIT NAMES .................................................................................................................................... 40
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL......................................................................................................................... 41
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS.............................................................................................. 42
TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS.............................................................................................. 42
TABLE 19: REGISTER MAP AND BIT NAMES - CHANNEL 2 REGISTERS.............................................................................................. 43
TABLE 20: REGISTER MAP AND BIT NAMES - CHANNEL 3 REGISTERS.............................................................................................. 43
TABLE 21: REGISTER MAP DESCRIPTION ........................................................................................................................................ 44
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 49
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 49
FIGURE 25. PRBS MODE ............................................................................................................................................................. 49
8.2 LOOPBACKS: ................................................................................................................................................ 49
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 49
FIGURE 26. ANALOG LOOPBACK..................................................................................................................................................... 50
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 50
FIGURE 27. DIGITAL LOOPBACK...................................................................................................................................................... 50
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 51
FIGURE 28. REMOTE LOOPBACK .................................................................................................................................................... 51
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 51
FIGURE 29. TRANSMIT ALL ONES (TAOS)...................................................................................................................................... 51
APPENDIX B .................................................................................................................... 52
TABLE 22: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 52
TABLE 23: TRANSFORMER DETAILS ................................................................................................................................................ 52
ORDERING INFORMATION .................................................................................................................. 54
PACKAGE DIMENSIONS - 176 PIN PACKAGE.................................................................................................. 54
REVISIONS................................................................................................................................................... 55
II
5 Page 
REV. 1.0.4
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
CLOCK INTERFACE
PIN #
SIGNAL NAME
69 E3CLK
67 DS3CLK
65 STS-1CLK/ 12M
156 SFM_EN
57 CLKOUTEN_0
54 CLKOUTEN_1
164 CLKOUTEN_2
167 CLKOUTEN_3
60 CLKOUT_0
63 CLKOUT_1
161 CLKOUT_2
158 CLKOUT_3
TYPE
I
I
I
I
O
O
DESCRIPTION
E3 Clock Input (34.368 MHz ± 20 ppm):
If any of the channels is configured in E3 mode, a reference clock 34.368 MHz
is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
DS3 Clock Input (44.736 MHz ± 20 ppm):
If any of the channels is configured in DS3 mode, a reference clock 44.736
MHz. is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
STS-1 Clock Input (51.84 MHz ± 20 ppm):
If any of the channels is configured in STS-1 mode, a reference clock 51.84
MHz is applied on this pin..
In Single Frequency Mode, a reference clock of 12.288 MHz ± 20 ppm is con-
nected to this pin and the internal clock synthesizer generates the appropriate
clock frequencies based on the configuration of the channels in E3, DS3 or
STS-1.
Single Frequency Mode Enable:
Tie this pin “High” to enable the Single Frequency Mode. A reference clock of
12.288 MHz ± 20 ppm is applied. This offers the flexibility of using a low cost
reference clock and configures the board for either E3 or DS3 or STS-1 without
the need to change any components on the board.
In the Single Frequency Mode (SFM) an output clock is provided for each chan-
nel if the CLK_EN bit is set thus eliminating the need for a separate clock
source for the framer.
Tie this pin “Low” if single frequency mode is not selected. In this case, the
appropriate reference clocks must be provided.
NOTE: This pin is internally pulled down
Clock output enable for channel 0
Clock output enable for channel 1
Clock output enable for channel 2
Clock output enable for channel 3
Pull this pin “High” to output low jitter clock on the CLKOUT_n pins.
NOTES:
1. This clock output is only available in SFM mode.
2. The maximum drive capability for the clockouts is 16 mA.
Clock output for channel 0
Clock output for channel 1
Clock output for channel 2
Clock output for channel 3
If CLKOUTEN_n pin is “High”, low jitter clock is output for each channel. Fre-
quency of these clocks is based on the mode (E3,DS3 or STS-1) the channels
are configured.
This eliminates the need for a separate clock source for the framer.
NOTES:
1. This clock output is only available in SFM mode.
2. The maximum drive capability for the clockouts is 16 mA.
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT75L04.PDF ] | |
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