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XRT75L06 데이터시트 PDF




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부품번호 XRT75L06 기능
기능 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT75L06 데이터시트, 핀배열, 회로
www.DataSheet4U.com
XRT75L06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
MARCH 2004
GENERAL DESCRIPTION
The XRT75L06 is a six channel fully integrated Line
Interface Unit (LIU) for E3/DS3/STS-1 applications.
The LIU incorporates 6 independent Receivers,
Transmitters and Jitter Attenuators in a single 217
Lead BGA package.
Each channel of the XRT75L06 can be independently
configured to operate in E3 (34.368 MHz), DS3
(44.736 MHz) or STS-1 (51.84 MHz). Each
transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT75L06’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT75L06 incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
REV. 1.0.3
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75L06 provides a Parallel Microprocessor
Interface for programming and control.
The XRT75L06 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
E3/DS3 Access Equipment
DSLAMs
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L06
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
RTIP_n
RRing_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
µProcessor Interface
XRT75L06
XRT75L06
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
MUX
Remote
LoopBack
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Channel 0
Channel n...
Channel 5
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TxON
PART NUMBER
XRT75L06IB
ORDERING INFORMATION
PACKAGE
217 Lead BGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT75L06 pdf, 반도체, 판매, 대치품
XRT75L06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.3
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS .............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT 75L06 ...................................................................................................... 1
ORDERING INFORMATION ................................................................................................................... 1
FEATURES .................................................................................................................................................... 2
TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2
Figure 2. XRT75L06 in BGA package (Bottom View) ....................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ........................................................................................................................................ 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
ANALOG POWER AND GROUND ................................................................................................................... 12
DIGITAL POWER AND GROUND ..................................................................................................................... 14
1.0 clock Synthesizer ............................................................................................................................. 16
1.1 CLOCK DISTRIBUTION ....................................................................................................................................... 16
Figure 4. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... 16
Figure 3. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 16
2.0 The Receiver Section ....................................................................................................................... 17
Figure 5. Receive Path Block Diagram ........................................................................................................... 17
2.1 RECEIVE LINE INTERFACE ................................................................................................................................. 17
Figure 6. Receive Line InterfaceConnection ................................................................................................... 17
2.2 ADAPTIVE GAIN CONTROL (AGC) ..................................................................................................................... 18
2.3 RECEIVE EQUALIZER ........................................................................................................................................ 18
Figure 7. ACG/Equalizer Blcok Diagram ......................................................................................................... 18
2.3.1 Recommendations for Equalizer Settings ....................................................................................... 18
2.4 CLOCK AND DATA RECOVERY .......................................................................................................................... 18
2.4.1 Data/Clock Recovery Mode ............................................................................................................... 18
2.4.2 Training Mode ..................................................................................................................................... 18
2.5 LOS (LOSS OF SIGNAL) DETECTOR .................................................................................................................. 19
2.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 19
2.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 19
TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 19
2.5.3 E3 LOS Condition: ............................................................................................................................. 20
Figure 8. Loss Of Signal Definition for E3 as per ITU-T G.775 ....................................................................... 20
Figure 9. Loss of Signal Definition for E3 as per ITU-T G.775. ....................................................................... 20
2.5.4 Interference Tolerance ....................................................................................................................... 21
Figure 10. Interference Margin Test Set up for DS3/STS-1 ............................................................................ 21
Figure 11. Interference Margin Test Set up for E3. ......................................................................................... 21
TABLE 2: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 22
2.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 23
2.6 B3ZS/HDB3 DECODER .................................................................................................................................... 23
Figure 12. Receiver Data output and code violation timing ............................................................................ 23
3.0 The Transmitter Section .................................................................................................................. 24
Figure 13. Transmit Path Block Diagram ........................................................................................................ 24
3.1 TRANSMIT DIGITAL INPUT INTERFACE ................................................................................................................ 24
Figure 14. Typical interface between terminal equipment and the XRT75L06 (dual-rail data) ....................... 24
Figure 15. Transmitter Terminal Input Timing ................................................................................................. 25
Figure 16. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 25
3.2 TRANSMIT CLOCK ............................................................................................................................................ 26
3.3 B3ZS/HDB3 ENCODER .................................................................................................................................... 26
I

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XRT75L06 전자부품, 판매, 대치품
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75L06
REV. 1.0.3
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
LEAD #
T15
R16
R15
N14
P14
P13
SIGNAL NAME
TxON_0
TxON_1
TxON_2
TxON_3
TxON_4
TxON_5
TYPE
DESCRIPTION
I Transmitter ON Input - Channel 0:
Transmitter ON Input - Channel 1:
Transmitter ON Input - Channel 2:
Transmitter ON Input - Channel 3:
Transmitter ON Input - Channel 4:
Transmitter ON Input - Channel 5:
These pins are active only when the corresponding TxON bits are set.
Table below shows the status of the transmitter based on theTxON bit and TxON
pin settings.
Bit Pin Transmitter Status
00
OFF
01
OFF
10
OFF
11
ON
E3 TxCLK_0
M3 TxCLK_1
F15 TxCLK_2
P16 TxCLK_3
G3 TxCLK_4
H15 TxCLK_5
NOTES:
1. These pins will be active and can control the TTIP and TRING outputs only
when the TxON_n bits in the channel register are set .
2. When Transmitters are turned off the TTIP and TRING outputs are Tri-
stated.
3. These pins are internally pulled up.
I Transmit Clock Input for TPOS and TNEG - Channel 0:
Transmit Clock Input for TPOS and TNEG - Channel 1:
Transmit Clock Input for TPOS and TNEG - Channel 2:
Transmit Clock Input for TPOS and TNEG - Channel 3:
Transmit Clock Input for TPOS and TNEG - Channel 4:
Transmit Clock Input for TPOS and TNEG - Channel 5:
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
By default, input data is sampled on the falling edge of TxCLK.
4

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