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XRT75R03D 데이터시트 PDF




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부품번호 XRT75R03D 기능
기능 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
제조업체 Exar Corporation
로고 Exar Corporation 로고


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XRT75R03D 데이터시트, 핀배열, 회로
XRT75R03D
EXAR DATA SHEET FORMAT TEMPLATES
MARCH 2006
REV. 1.0.4
GENERAL DESCRIPTION
The XRT75R03D is a three-channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R3
Technology (Reconfigurable, Relayless Redundancy)
with Jitter Attenuator for E3/DS3/STS-1 applications.
It incorporates 3 independent Receivers,
Transmitters and Jitter Attenuators in a single 128 pin
LQFP package.
Each channel of the XRT75R03D can be
independently configured to operate in the data rate,
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz). Each transmitter can be turned off and tri-
stated for redundancy support or for conserving
power.
The XRT75R03D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75R03D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75R03D provides both Serial
Microprocessor Interface as well as Hardware mode
for programming and control.
The XRT75R03D supports local, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
FEATURES
RECEIVER:
R3 Technology (Reconfigurable, Relayless
Redundancy)
On chip Clock and Data Recovery circuit for high
input jitter tolerance
Meets E3/DS3/STS-1 Jitter Tolerance Requirement
Detects and Clears LOS as per G.775
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
Provides low jitter output clock
TRANSMITTER:
R3 Technology (Reconfigurable, Relayless
Redundancy)
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Each Transmitter can be independently turned on
or off
Transmitters provide Voltage Output Drive
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator for
each channel
Jitter Attenuator can be selected in Receive or
Transmit paths
Meets ETSI TBR 24 Jitter Transfer Requirements
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
Jitter Attenuator can be disabled
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration
Supports optional internal Transmit driver
monitoring
Hardware Mode for control and configuration
Each channel supports Local, Remote and Digital
Loop-backs
Single 3.3 V ± 5% power supply
5 V Tolerant I/O
Available in 128 pin LQFP
- 40°C to 85°C Industrial Temperature Range
APPLICATIONS
E3/DS3 Access Equipment
STS1-SPE to DS3 De-Synchronizing
DSLAMs
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT75R03D pdf, 반도체, 판매, 대치품
XRT75R03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER REV. 1.0.4
GENERAL DESCRIPTION .................................................................................................1
FEATURES .....................................................................................................................................................1
APPLICATIONS ................................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R03D ........................................................................................................................... 2
TRANSMIT INTERFACE CHARACTERISTICS........................................................................................................2
RECEIVE INTERFACE CHARACTERISTICS..........................................................................................................2
FIGURE 2. PIN OUT OF THE XRT75R03D......................................................................................................................................... 3
ORDERING INFORMATION.....................................................................................................................3
PIN DESCRIPTIONS (BY FUNCTION) ..............................................................................4
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS .......................................................................4
TRANSMIT LINE SIDE PINS..............................................................................................................................8
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS ......................................................................10
RECEIVE LINE SIDE PINS ..............................................................................................................................17
GENERAL CONTROL PINS .............................................................................................................................18
CONTROL AND ALARM INTERFACE.................................................................................................................20
JITTER ATTENUATOR INTERFACE...................................................................................................................20
POWER SUPPLY AND GROUND PINS .............................................................................................................22
XRT75R03D PIN LISTING IN NUMERICAL ORDER..........................................................................................24
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ........................................29
1.1 NETWORK ARCHITECTURE ......................................................................................................................... 29
FIGURE 3. NETWORK REDUNDANCY ARCHITECTURE ...................................................................................................................... 29
1.2 POWER FAILURE PROTECTION .................................................................................................................. 29
1.3 SOFTWARE VS HARDWARE AUTOMATIC PROTECTION SWITCHING ................................................... 29
2.0 ELECTRICAL CHARACTERISTICS ....................................................................................................31
TABLE 1: ABSOLUTE MAXIMUM RATINGS......................................................................................................................................... 31
TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................................................ 31
3.0 TIMING CHARACTERISTICS ..............................................................................................................32
FIGURE 4. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75R03D (DUAL-RAIL DATA) ....................................... 32
FIGURE 5. TRANSMITTER TERMINAL INPUT TIMING .......................................................................................................................... 32
FIGURE 6. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ................................................................................................... 33
FIGURE 7. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES................................................................. 33
4.0 LINE SIDE CHARACTERISTICS: ........................................................................................................34
4.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 34
FIGURE 8. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703 ......................................................................... 34
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS........................................................ 35
FIGURE 9. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS............................. 36
TABLE 4: STS-1 PULSE MASK EQUATIONS ..................................................................................................................................... 36
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) .............................. 37
FIGURE 10. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ................................................................... 37
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 38
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 38
FIGURE 11. MICROPROCESSOR SERIAL INTERFACE STRUCTURE...................................................................................................... 39
FIGURE 12. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 39
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) .................................. 39
FUNCTIONAL DESCRIPTION: ........................................................................................41
5.0 THE TRANSMITTER SECTION: ..........................................................................................................41
FIGURE 13. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) ............................................................ 41
FIGURE 14. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED) ............................................................................. 41
5.1 TRANSMIT CLOCK: ....................................................................................................................................... 42
5.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 42
5.2.1 B3ZS ENCODING: ...................................................................................................................................................... 42
FIGURE 15. B3ZS ENCODING FORMAT ........................................................................................................................................... 42
5.2.2 HDB3 ENCODING:...................................................................................................................................................... 42
FIGURE 16. HDB3 ENCODING FORMAT .......................................................................................................................................... 42
5.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 43
5.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 43
5.3.2 INTERFACING TO THE LINE: .................................................................................................................................... 43
5.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 44
FIGURE 17. TRANSMIT DRIVER MONITOR SET-UP. ........................................................................................................................... 44
5.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 44
I

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XRT75R03D 전자부품, 판매, 대치품
XRT75R03D
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
10.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................. 118
10.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE XRT75R03D IN A TYPICAL
SYSTEM APPLICATION .............................................................................................................................. 118
10.7.1 INTRINSIC JITTER TEST RESULTS...................................................................................................................... 118
TABLE 32: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS................................... 118
10.7.2 WANDER MEASUREMENT TEST RESULTS........................................................................................................ 120
10.8 DESIGNING WITH THE XRT75R03D ......................................................................................................... 120
10.8.1 HOW TO DESIGN AND CONFIGURE THE XRT75R03D TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED
INTRINSIC JITTER AND WANDER REQUIREMENTS .............................................................................................. 120
FIGURE 58. ILLUSTRATION OF THE XRT75R03D BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS ......... 120
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06................................................... 121
CHANNEL 1 ADDRESS LOCATION = 0X0E........................................... 121
CHANNEL 2 ADDRESS LOCATION = 0X16 ........................................... 121
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06................................................... 122
CHANNEL 1 ADDRESS LOCATION = 0X0E................................................ 122
CHANNEL 2 ADDRESS LOCATION = 0X16 ................................................. 122
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07................................. 122
CHANNEL 1 ADDRESS LOCATION = 0X0F.................................... 122
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 122
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................. 123
CHANNEL 1 ADDRESS LOCATION = 0X0F.............................. 123
CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 123
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................. 123
CHANNEL 1 ADDRESS LOCATION = 0X0F............................. 123
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 123
10.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRI-
OR TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE XRT75R03D . 123
FIGURE 59. ILLUSTRATION OF MINOR PATTERN P1 .................................................................................................................. 124
FIGURE 60. ILLUSTRATION OF MINOR PATTERN P2 .................................................................................................................. 125
FIGURE 61. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A ................................................ 125
FIGURE 62. ILLUSTRATION OF MINOR PATTERN P3 .................................................................................................................. 126
FIGURE 63. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B............................................................. 126
FIGURE 64. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC ............................. 127
FIGURE 65. SIMPLE ILLUSTRATION OF THE XRT75R03D BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION ................... 127
10.8.3 HOW DOES THE XRT75R03D PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME RE-
QUIREMENTS OF 50MS (PER TELCORDIA GR-253-CORE)? ................................................................................. 127
TABLE 33: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ....................................................................... 128
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................. 129
CHANNEL 1 ADDRESS LOCATION = 0X0F............................. 129
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 129
10.8.4 HOW SHOULD ONE CONFIGURE THE XRT75R03D, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT
THE END CUSTOMER'S SITE? .................................................................................................................................. 129
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................. 129
CHANNEL 1 ADDRESS LOCATION = 0X0F.................................... 129
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 129
ORDERING INFORMATION ................................................................................................................ 130
PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE ............................................................................... 130
REVISIONS................................................................................................................................................. 131
IV

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관련 데이터시트

부품번호상세설명 및 기능제조사
XRT75R03

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation
XRT75R03D

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation

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