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XRT75R12 데이터시트 PDF




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부품번호 XRT75R12 기능
기능 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT75R12 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PRELIMINARY
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
OCTOBER 2003
GENERAL DESCRIPTION
The XRT75R12 is a twelve channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R3
Technology (Reconfigurable, Relayless Redundancy)
for E3/DS3/STS-1 applications. The LIU incorporates
12 independent Receivers, Transmitters and Jitter
Attenuators in a single 420 Lead TBGA package.
Each channel of the XRT75R12 can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT75R12’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT75R12 incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
REV. P1.0.2
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75R12 provides a Parallel Microprocessor
Interface for programming and control.
The XRT75R12 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
E3/DS3 Access Equipment
DSLAMs
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R12
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
RTIP_n
RRing_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
µProcessor Interface
XRT75R12
XRT75R12
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
MUX
Remote
LoopBack
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Channel 0
Channel n...
Channel 11
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TxON
PART NUMBER
XRT75R12IB
ORDERING INFORMATION
PACKAGE
420 Lead TBGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT75R12 pdf, 반도체, 판매, 대치품
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. P1.0.2
PRELIMINARY
FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED).................................................................................... 29
FIGURE 18. B3ZS ENCODING FORMAT ................................................................................................................................................. 29
4.4 TRANSMIT PULSE SHAPER ......................................................................................................................... 30
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT.............................................................................................................................. 30
4.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................. 30
FIGURE 19. HDB3 ENCODING FORMAT ................................................................................................................................................. 30
4.5 E3 LINE SIDE PARAMETERS ........................................................................................................................ 31
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703 ............................................................................. 31
TABLE 4: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .............................................................. 32
FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ................................. 33
TABLE 5: STS-1 PULSE MASK EQUATIONS ........................................................................................................................................... 33
TABLE 6: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)..................................... 34
FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ......................................................................... 34
TABLE 8: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ........................................ 35
TABLE 7: DS3 PULSE MASK EQUATIONS............................................................................................................................................... 35
4.6 TRANSMIT DRIVE MONITOR ........................................................................................................................ 36
4.7 TRANSMITTER SECTION ON/OFF ............................................................................................................... 36
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP................................................................................................................................... 36
5.0 JITTER ..................................................................................................................................................37
5.1 JITTER TOLERANCE ..................................................................................................................................... 37
5.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS ................................................................................................ 37
FIGURE 25. JITTER TOLERANCE MEASUREMENTS .................................................................................................................................. 37
5.1.2 E3 JITTER TOLERANCE REQUIREMENTS .............................................................................................................. 38
FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1 ...................................................................................................................... 38
FIGURE 27. INPUT JITTER TOLERANCE FOR E3..................................................................................................................................... 38
5.2 JITTER TRANSFER ........................................................................................................................................ 39
5.3 JITTER ATTENUATOR ................................................................................................................................... 39
TABLE 9: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ........................................................................... 39
TABLE 10: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................................................... 39
5.3.1 JITTER GENERATION................................................................................................................................................ 40
TABLE 11: JITTER TRANSFER PASS MASKS ........................................................................................................................................... 40
FIGURE 28. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE ...................................................................... 40
6.0 DIAGNOSTIC FEATURES ...................................................................................................................41
6.1 PRBS GENERATOR AND DETECTOR ......................................................................................................... 41
FIGURE 29. PRBS MODE ................................................................................................................................................................... 41
6.2 LOOPBACKS .................................................................................................................................................. 42
6.2.1 ANALOG LOOPBACK ................................................................................................................................................ 42
FIGURE 30. ANALOG LOOPBACK ........................................................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ................................................................................................................................................. 43
6.2.3 REMOTE LOOPBACK ................................................................................................................................................ 43
FIGURE 31. DIGITAL LOOPBACK ............................................................................................................................................................ 43
FIGURE 32. REMOTE LOOPBACK ........................................................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) ...................................................................................................................... 44
FIGURE 33. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 44
7.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................45
TABLE 12: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 45
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 45
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 46
TABLE 13: XRT75R12 MICROPROCESSOR INTERFACE SIGNALS ............................................................................................................ 46
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 47
TABLE 14: ASYNCHRONOUS TIMING SPECIFICATIONS............................................................................................................................. 48
FIGURE 35. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................................. 48
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................................... 49
TABLE 15: SYNCHRONOUS TIMING SPECIFICATIONS............................................................................................................................... 49
7.3 REGISTER MAP ............................................................................................................................................. 50
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R12............................................................................................ 50
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................................ 59
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................................... 59
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS........................................................................................................ 59
TABLE 18: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ..................................................... 59
TABLE 19: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR8 (ADDRESS LOCATION = 0X08) ..................................................... 60
TABLE 20: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR96 (ADDRESS LOCATION = 0X60) ......................................................... 61
TABLE 21: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0)....................................................... 62
II

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XRT75R12 전자부품, 판매, 대치품
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12
REV. P1.0.2
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
C25
AB25
H23
W23
H24
Y26
H3
Y1
H4
W4
C2
AB2
TxNEG0
TxNEG1
TxNEG2
TxNEG3
TxNEG4
TxNEG5
TxNEG6
TxNEG7
TxNEG8
TxNEG9
TxNEG10
TxNEG11
I Transmit Negative Data Input
When a Channel has been configured to operate in the Dual-Rail Mode,
the user should apply a pulse to this input pin anytime the Transmit Section
of the LIU IC to generate a negative-polarity pulse onto the line. This signal
will be latched into the Transmit Section circuitry upon the active edge of
the TxCLK_n signal.
NOTE: In the Single-Rail Mode, this input pin has no function, and should
be tied to GND.
B24
AE24
C20
AD20
C16
AD16
C11
AD11
C7
AD7
C3
AD3
TTip0
TTip1
TTip2
TTip3
TTip4
TTip5
TTip6
TTip7
TTip8
TTip9
TTip10
TTip11
O Transmit TTIP Output - Positive Polarity Signal
These output pins along with the corresponding TRING_n output pins, function as
the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel of the
XRT75R12.
Connect this signal and the corresponding TRING_n output signal to a 1:1 trans-
former.
Whenever the Transmit Section of the Channel generates and transmits a positive-
polarity pulse onto the line, this output pin will be pulsed to a high ervoltage than
its corresponding TRING_n output pins.
Conversely, whenever the Transmit Section of the Channel generates and transmit
a negative-polarity pulse onto the line, this output pin will be pulsed to a lower
voltage than its corresponding TRING_n output pin.
NOTE: This output pin will be tri-stated whenever the TxON input pin or bit-field
is set to "0".
C24
AD24
B20
AE20
B16
AE16
B11
AE11
B7
AE7
B3
AE3
TRing0
TRing1
TRing2
TRing3
TRing4
TRing5
TRing6
TRing7
TRing8
TRing9
TRing10
TRing11
O Transmit Ring Output - Negative Polarity Signal
These output pins along with the corresponding TTIP_n output pins, function as
the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel, within
the XRT75R12.
Connect this signal and the corresponding TTIP_n output signal to a 1:1 trans-
former.
Whenever the Transmit Section of the Channel generates and transmits a positive-
polarity pulse onto the line, this output pin will be pulsed to a lower voltage than its
corresponding TTIP_n output pin.
Conversely, whenever the Transmit Section of the Channel generates and transmit
a negative-polarity pulse onto the line, this output pin will be pulsed to a higher
voltage than its corresponding TTIP_n output pin.
NOTE: This output pin will be tri-stated whenever the TxON input pin or bit-field
is set to "0".
4

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