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PDF XRT75R12D Data sheet ( Hoja de datos )
| Número de pieza | XRT75R12D | |
| Descripción | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
OCTOBER 2003
GENERAL DESCRIPTION
The XRT75R12D is a twelve channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R3
Technology (Reconfigurable, Relayless Redundancy)
for E3/DS3/STS-1 applications. The LIU incorporates
12 independent Receivers, Transmitters and Jitter
Attenuators in a single 420 Lead TBGA package.
Each channel of the XRT75R12D can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT75R12D’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT75R12D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
REV. P1.0.1
Bellcore GR-499 specifications. Also, the jitter
attenuators can be used for clock smoothing in
SONET STS-1 to DS-3 de-mapping.
The XRT75R12D provides a Parallel Microprocessor
Interface for programming and control.
The XRT75R12D supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
• E3/DS3 Access Equipment
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R12D
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
RTIP_n
RRing_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
µProcessor Interface
XRT75R12D
XRT75R12D
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
MUX
Remote
LoopBack
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Channel 0
Channel n...
Channel 11
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TxON
PART NUMBER
XRT75R12DIB
ORDERING INFORMATION
PACKAGE
420 Lead TBGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PRELIMINARY
REV. P1.0.1
TABLE 22: THE ABOVE IS: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61) .................................. 63
TABLE 23: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)....................................................... 63
TABLE 24: DEVICE/PART NUMBER REGISTER - CR110 (ADDRESS LOCATION = 0X6E) ........................................................................... 64
TABLE 25: CHIP REVISION NUMBER REGISTER - CR111 (ADDRESS LOCATION = 0X6F) ......................................................................... 64
THE PER-CHANNEL REGISTERS........................................................................................................................... 65
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................................... 66
TABLE 26: XRT75R12D REGISTER MAP SHOWING INTERRUPT ENABLE REGISTERS (IER_N) ............................................................... 66
TABLE 27: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL N ADDRESS LOCATION = 0XM1 .................................................... 66
TABLE 28: XRT75R12D REGISTER MAP SHOWING INTERRUPT STATUS REGISTERS (ISR_N) ............................................................... 68
TABLE 29: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2 .................................................... 68
TABLE 30: XRT75R12D REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N)........................................................................ 70
TABLE 31: ALARM STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM3................................................................................... 70
TABLE 32: XRT75R12D REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N) ................................................................ 74
TABLE 33: TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4 ........................................................................... 74
TABLE 34: XRT75R12D REGISTER MAP SHOWING RECEIVE CONTROL REGISTERS (RC_N).................................................................. 76
TABLE 35: RECEIVE CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM5 ............................................................................. 76
TABLE 36: XRT75R12D REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_N)................................................................. 77
TABLE 37: CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6 ............................................................................ 77
TABLE 38: XRT75R12D REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N)................................................. 80
TABLE 39: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM7 ........................................................... 80
TABLE 40: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N) ..................................................... 81
TABLE 41: ERROR COUNTER MSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMA................................................................. 81
TABLE 42: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER LSBYTE REGISTERS (EL_N) ....................................................... 82
TABLE 43: ERROR COUNTER LSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMB.................................................................. 82
TABLE 44: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N) ..................................................... 82
TABLE 45: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC ................................................................ 83
8.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ............................................................... 85
8.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 85
FIGURE 37. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ............... 86
8.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 87
8.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 87
FIGURE 38. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME ..................................................................................................... 88
FIGURE 39. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
89
FIGURE 40. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 90
FIGURE 41. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 91
FIGURE 42. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE ............................................................................................. 92
FIGURE 43. AN ILLUSTRATION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE ......... 93
FIGURE 44. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN
STS-1 SPE.......................................................................................................................................................................... 93
8.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 94
FIGURE 45. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .................................... 95
FIGURE 46. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3 SIGNAL
THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL .................................................................................. 96
8.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS .............................................................................. 98
8.3.1 THE CONCEPT OF AN STS-1 SPE POINTER........................................................................................................... 98
FIGURE 47. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL
THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL................................................................................... 98
FIGURE 48. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES ........................................... 99
8.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK ................................................................................ 100
FIGURE 49. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION OF
THE J1 BYTE, DESIGNATED .................................................................................................................................................. 100
FIGURE 50. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES)
AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME ................................................ 100
8.3.3 CAUSES OF POINTER ADJUSTMENTS ................................................................................................................. 101
FIGURE 51. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER.................................................................. 102
FIGURE 52. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DES-
IGNATED ............................................................................................................................................................................. 103
FIGURE 53. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS DES-
IGNATED ............................................................................................................................................................................. 104
8.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ............................................................................. 105
8.4 CLOCK GAPPING JITTER ........................................................................................................................... 105
FIGURE 54. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION ...................................... 105
8.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
III
5 Page 
PRELIMINARY
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. P1.0.1
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
D25
AD25
G23
AA24
J24
U24
J3
U3
G4
AA3
D2
AD2
RLOS0
RLOS1
RLOS2
RLOS3
RLOS4
RLOS5
RLOS6
RLOS7
RLOS8
RLOS9
RLOS10
RLOS11
O Receive Loss of Signal Output Indicator
This output pin indicates Loss of Signal (LOS) Defect condition for the corre-
sponding channel.
"Low" - Indicates that the corresponding Channel is NOT currently declaring the
LOS defect condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOS
defect condition.
G22
AB26
K22
U22
L24
W25
L3
W2
K5
U5
G5
AB1
RLOL0
RLOL1
RLOL2
RLOL3
RLOL4
RLOL5
RLOL6
RLOL7
RLOL8
RLOL9
RLOL10
RLOL11
O Receive Loss of Lock Output Indicator
This output pin indicates Loss of Lock (LOL) condition for the corresponding
channel.
"Low" - Indicates that the corresponding Channel is NOT declaring the LOL
condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOL
condition.
NOTE: The Receive Section of a given channel will declare the LOL condition
anytime the frequency of the Recovered Clock (RCLK) signal differs
from that of the reference clock programmed for that channel by 0.5%
or more.
E25
AD26
G24
Y24
L22
T22
L5
T5
G3
Y3
E2
AD1
RxPOS0
RxPOS1
RxPOS2
RxPOS3
RxPOS4
RxPOS5
RxPOS6
RxPOS7
RxPOS8
RxPOS9
RxPOS10
RxPOS11
O Receive Positive Data Output
The function of these output pins depends upon whether the channel has been
configured to operate in the Single-Rail or Dual-Rail Mode.
Dual-Rail Mode - Receive Positive Polarity Data Output
If the channel has been configured to operate in the Dual-Rail Mode, then all
positive-polarity data will be output via this pin. The negative-polarity data will
be output via the corresponding RxNEG_n pin. In other words, the Receive
Section of the corresponding Channel will pulse this output pin "High" for one
period of RCLK_n anytime it receives a positive-polarity pulse via the RTIP/
RRING input pins.
The data output via this pin is updated upon the active edge of RxCLK_n output
clock signal.
Single-Rail Mode - Receive Data Output
In the Single-Rail Mode, all Receive (or Recovered) data will be output via this
pin.
The data output via this pin is updated upon the active edge of the RCLK_n
output clock signal.
6
11 Page | ||
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| PDF Descargar | [ Datasheet XRT75R12D.PDF ] | |
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