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XRT75VL00D 데이터시트 PDF




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부품번호 XRT75VL00D 기능
기능 E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT75VL00D 데이터시트, 핀배열, 회로
www.DataSheet4U.com
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FEBRUARY 2004
GENERAL DESCRIPTION
The XRT75VL00D is a single-channel fully integrated
Line Interface Unit (LIU) with Sonet Desynchronizer
for E3/DS3/STS-1 applications. It incorporates an
independent Receiver, Transmitter and Jitter
Attenuator in a single 52 pin TQFP package.
The XRT75VL00D can be configured to operate in
either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes. The transmitter can be turned
off (tri-stated) for redundancy support and for
conserving power.
The XRT75VL00D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75VL00D incorporates an advanced crystal-
less jitter attenuator that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications. Also, the jitter attenuator can
be used for clock smoothing in SONET STS-1 to DS3
de-mapping.
The XRT75VL00D provides both Serial
Microprocessor Interface as well as Hardware mode
for programming and control.
The XRT75VL00D supports local, remote and digital
loop-backs. The XRT75VL00D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets E3/DS3/STS-1
Requirements.
Jitter
Tolerance
Detects and Clears LOS as per G.775.
Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards.
Meets ETSI TBR 24 Jitter Transfer Requirements.
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
REV. 1.0.3
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
Provides low jitter output clock.
TRANSMITTER:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitter can be turned on or off.
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator.
Jitter Attenuator can be selected in Receive or
Transmit paths.
16, 32 or 128 bits selectable FIFO size.
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
Jitter Attenuator can be disabled.
De-Synchronizer for SONET STS-1 to DS-3
demapping.
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration.
Supports optional internal Transmit Driver
Monitoring.
PRBS error counter register to accumulate errors.
Hardware Mode for control and configuration.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V ± 5% power supply.
5 V Tolerant I/O.
Available in 52 pin TQFP.
-40°C to 85°C Industrial Temperature Range.
APPLICATIONS
E3/DS3 Access Equipment.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
Fiber Optic Terminals.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT75VL00D pdf, 반도체, 판매, 대치품
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE OF CONTENTS
REV. 1.0.3
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2
Figure 1. Block Diagram of the XRT 75VL00D ................................................................................................. 2
JITTER ATTENUATORS ................................................................................................................................... 3
Figure 2. Pin Out of the XRT75VL00D .............................................................................................................. 3
ORDERING INFORMATION ................................................................................................................... 3
TABLE OF CONTENTS ................................................................................................................................... 1
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ........................................................................................................................................ 8
OPERATING MODE SELECT ........................................................................................................................... 9
CONTROL AND ALARM INTERFACE ................................................................................................................. 9
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE) ........................................................................ 11
13
JITTER ATTENUATOR INTERFACE ................................................................................................................. 13
ANALOG POWER AND GROUND ................................................................................................................... 14
DIGITAL POWER AND GROUND ................................................................................................................... 14
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 15
TABLE 1: ABSOLUTE MAXIMUM RATINGS ............................................................................................................ 15
TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................... 15
2.0 TIMING CHARACTERISTICS ............................................................................................................ 16
Figure 3. Typical interface between terminal equipment and the XRT75VL00D (dual-rail data) .................... 16
Figure 4. Transmitter Terminal Input Timing ................................................................................................... 16
Figure 5. Receiver Data output and code violation timing .............................................................................. 17
Figure 6. Transmit Pulse Amplitude test circuit for E3, DS3 and STS-1 Rates ............................................... 17
3.0 LINE SIDE CHARACTERISTICS: ..................................................................................................... 18
3.1 E3 LINE SIDE PARAMETERS: ............................................................................................................................. 18
Figure 7. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ..................................................... 18
TABLE 3: E3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3 V ± 5%) ....... 18
Figure 8. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ............ 19
TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 19
TABLE 5: STS-1 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD =3.3V ± 5%) 20
Figure 9. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 .................................................. 20
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 21
TABLE 7: DS3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3V ± 5%) ... 21
Figure 10. Microprocessor Serial Interface Structure ...................................................................................... 22
Figure 11. Timing Diagram for the Microprocessor Serial Interface ................................................................ 22
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) ..... 23
4.0 The Transmitter Section: ................................................................................................................. 24
4.1 TRANSMIT CLOCK: ........................................................................................................................................... 24
4.2 B3ZS/HDB3 ENCODER: .................................................................................................................................. 24
4.2.1 B3ZS Encoding: ................................................................................................................................. 24
Figure 12. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 24
Figure 13. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 24
4.2.2 HDB3 Encoding: ................................................................................................................................. 25
4.3 TRANSMIT PULSE SHAPER: .............................................................................................................................. 25
Figure 14. B3ZS Encoding Format ................................................................................................................. 25
Figure 15. HDB3 Encoding Format ................................................................................................................. 25
4.3.1 Guidelines for using Transmit Build Out Circuit: ............................................................................ 26
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XRT75VL00D 전자부품, 판매, 대치품
REV. 1.0.3
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
Figure 53. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................... 72
9.5.8 Continuous Pattern ............................................................................................................................ 73
9.5.9 Continuous Add ................................................................................................................................ 73
Figure 54. Illustration of Continuous Periodic Pointer Adjustment Scenario ................................................. 73
9.5.10 Continuous Cancel .......................................................................................................................... 74
Figure 55. Illustration of Continuous-Add Pointer Adjustment Scenario ......................................................... 74
Figure 56. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................... 74
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................................... 75
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM APPLICATION ...
75
9.7.1 Intrinsic Jitter Test results ................................................................................................................ 75
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ....... 75
9.7.2 Wander Measurement Test Results ................................................................................................. 76
9.8 DESIGNING WITH THE LIU ................................................................................................................................. 76
9.8.1 How to design and configure the LIU to permit a system to meet the above-mentioned Intrinsic
Jitter and Wander requirements ...................................................................................................................................... 76
Figure 57. Illustration of the LIU being connected to a Mapper IC for SONET De-Sync Applications ........... 76
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 77
CHANNEL 1 ADDRESS LOCATION = 0X0E ........................................... 77
CHANNEL 2 ADDRESS LOCATION = 0X16 ........................................... 77
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 78
CHANNEL 1 ADDRESS LOCATION = 0X0E ................................................ 78
CHANNEL 2 ADDRESS LOCATION = 0X16 ................................................. 78
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ................................. 78
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................... 78
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 78
9.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to
routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU ............................................................... 79
SOME NOTES PRIOR TO STARTING THIS DISCUSSION: 79
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 79
CHANNEL 1 ADDRESS LOCATION = 0X0F .............................. 79
CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 79
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 79
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................. 79
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 79
OUR PRE-PROCESSING RECOMMENDATIONS 80
Figure 58. Illustration of MINOR PATTERN P1 .............................................................................................. 80
Figure 59. Illustration of MINOR PATTERN P2 .............................................................................................. 81
Figure 60. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A ................................ 81
Figure 61. Illustration of MINOR PATTERN P3 .............................................................................................. 82
Figure 62. Illustration of Procedure which is used to Synthesize PATTERN B ............................................. 82
9.8.3 How does the LIU permit the user to comply with the SONET APS Recovery Time requirements
of 50ms (per Telcordia GR-253-CORE)? ......................................................................................................................... 83
Figure 63. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC .............. 83
Figure 64. Simple Illustration of the LIU being used in a SONET De-Synchronizer" Application ................... 83
TABLE 20: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ............................................ 84
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 84
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................. 84
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 84
9.8.4 How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Cus-
tomer’s site? ..................................................................................................................................................................... 85
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 85
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................... 85
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 85
ORDERING INFORMATION ............................................................................................................................ 86
PACKAGE DIMENSIONS ................................................................................................. 86
4

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관련 데이터시트

부품번호상세설명 및 기능제조사
XRT75VL00

E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation
XRT75VL00D

E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation
Exar Corporation

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