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XRT79L72 데이터시트 PDF




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부품번호 XRT79L72 기능
기능 2-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
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XRT79L72 데이터시트, 핀배열, 회로
xrwww.DataSheet4U.com
PRELIMINARY
XRT79L72
FEBRUARY 2005
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
REV. P1.0.2
HARDWARE MANUAL
The XRT79L72 is a two channel, ATM UNI/PPP
Physical Layer Processor with integrated DS3/E3
framing controllers and Line Interface Units with Jitter
Attenuators that are designed to support ATM direct
mapping and cell delineation as well as PPP mapping
and Frame processing. For ATM UNI applications,
this device provides the ATM Physical Layer (Physi-
cal Medium Dependent and Transmission Conver-
gence sub-layers) interface for the public and private
networks at DS3/E3 rates. For Clear-Channel Framer
applications, this device supports the transmission
and reception of “user data” via the DS3/E3 payload.
The XRT79L72 includes DS3/E3 Framing, Line Inter-
face Unit with Jitter Attenuator that supports mapping of
ATM or HDLC framed data. A flexible parallel micropro-
cessor interface is provided for configuration and con-
trol. Industry standard UTOPIA II and POS-PHY inter-
face are also provided.
GENERAL FEATURES:
Integrated T3/E3 Line Interface Unit
Integrated Jitter Attenuator that can be selected
either in Receive or Transmit path
Flexible integrated Clock Multiplier that takes single
frequency clock and generates either DS3 or E3
frequency.
8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
HDLC Controller that provides the mapping/extrac-
tion of either bit or byte mapped encapsulated
packet from DS3/E3 Frame.
Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
Supports ATM cell or PPP Packet Mapping
Supports M13 and C-Bit Parity Framing Formats
Supports DS3/E3 Clear-Channel Framing.
Includes PRBS Generator and Receiver
Supports Line, Cell, and PLCP Loop-backs
Interfaces to 8 Bit wide Intel, Motorola or PowerPC
Low power 3.3V, 5V Input Tolerant, CMOS
Available in 456 Lead PBGA Package
JTAG Interface
LINE INTERFACE UNIT
On chip Clock and Data Recovery circuit for high
input jitter tolerance
Meets E3/DS3 Jitter Tolerance Requirements
Detects and Clears LOS as per G.775.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
Meets ETSI TBR 24 and GR-499 Jitter Transfer
Requirements
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
On chip advanced crystal-less Jitter Attenuator
Jitter Attenuator can be selected in Receive or
Transmit paths
16 or 32 bits selectable FIFO size
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards
Jitter Attenuator can be disabled
Maximum power consumption 1.7W
DS3/E3 FRAMER
DS3 framer supports both M13 and C-bit parity.
DS3 framer meets ANSI T1.107 and T1.404 stan-
dards.
Detects OOF,LOF,AIS,RDI/FERF alarms.
Generation and Insertion of FEBE on received par-
ity errors supported.
Automatic insertion of RDI/FERF on alarm status.
E3 framer meets G.832,G.751 standards.
Framers can be bypassed.
ATM/PPP PROTOCOL PROCESSOR
TRANSMIT CELL PROCESSING
Extracts ATM cells
Supports ATM cell payload scrambling
Maps ATM cells into E3 or DS3 frame
PLCP frame and mapping of ATM cell streams
RECEIVE CELL PROCESSING
Extraction of ATM cells from PLCP frame or directly
from E3 or DS3 frame
Termination of PLCP frame
Supports payload cell de-scrambling
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT79L72 pdf, 반도체, 판매, 대치품
XRT79L72
REV. P1.0.2
PRELIMINARY
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TABLE OF CONTENTS
HARDWARE MANUAL ......................................................................................................1
GENERAL FEATURES:......................................................................................................................................1
Line Interface Unit ....................................................................................................................................................... 1
DS3/E3 Framer............................................................................................................................................................ 1
ATM/PPP PROTOCOL PROCESSOR........................................................................................................................ 1
Transmit Cell Processing............................................................................................................................................. 1
Receive Cell Processing.............................................................................................................................................. 1
Transmit Packet Processing ........................................................................................................................................ 2
Receive Packet Processing ......................................................................................................................................... 2
Utopia/ System Interface ............................................................................................................................................. 2
Serial Interface ............................................................................................................................................................ 2
APPLICATIONS ...........................................................................................................................................2
FIGURE 1. BLOCK DIAGRAM OF THE XRT79L72 ............................................................................................................................... 2
PRODUCT ORDERING INFORMATION ................................................................................................................3
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS.........................................................................................................................................4
MICROPROCESSOR INTERFACE .......................................................................................................................4
TEST AND DIAGNOSTIC ...................................................................................................................................6
GENERAL PURPOSE INPUT AND OUTPUT PINS.................................................................................................7
TRANSMIT SYSTEM SIDE INTERFACE PINS.......................................................................................................7
RECEIVE SYSTEM SIDE INTERFACE PINS.......................................................................................................24
TRANSMIT LINE SIDE SIGNALS ......................................................................................................................39
RECEIVE LINE SIDE SIGNALS ........................................................................................................................41
ELECTRICAL CHARACTERISTICS ................................................................................46
TABLE 1: DC ELECTRICAL CHARACTERISTICSS..................................................................................................................... 46
Applies to all TTL-Level Input and CMOS Level Output pins - Ambient Temperature = 25°C .................................. 46
AC ELECTRICAL CHARACTERISTIC INFORMATION ..................................................46
MICROPROCESSOR INTERFACE TIMING FOR REVISION A SILICON ......................................................46
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS INTEL MODE.................................................... 46
FIGURE 2. ASYNCHRONUS MODE 1 - INTEL TYPE PROGRAMMED I/O TIMING (WRITE CYCLE) ............................................................ 46
FIGURE 3. ASYNCHRONUS MODE 1 - INTEL TYPE PROGRAMMED I/O TIMING (READ CYCLE) ............................................................. 47
TABLE 2: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE INTEL ASYNCHRONOUS
MODE ............................................................................................................................................................................ 47
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K)
MODE................................................................................................................................ 48
FIGURE 4. ASYNCHRONUS MODE 2 - MOTOROLA 68K PROGRAMMED I/O TIMING (WRITE CYCLE) .................................................... 48
FIGURE 5. ASYNCHRONUS MODE 2 - MOTOROLA 68 PROGRAMMED I/O TIMING (READ CYCLE) ........................................................ 48
TABLE 3: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE WHEN CONFIGURED TO OPERATE IN THE MOTOROLA (68K) ASYN-
CHRONOUS MODE........................................................................................................................................................... 49
MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE49
FIGURE 6. SYNCHRONOUS MODE 3 - IBM POWERPC 403 INTERFACE TIMING (WRITE CYCLE) ......................................................... 49
FIGURE 7. SYNCHRONOUS MODE 3 - IBM POWERPC 403 INTERFACE TIMING (READ CYCLE)........................................................... 50
TABLE 4: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE IBM POWER PC403
MODE ............................................................................................................................................................................ 50
DS3/E3 LIU INTERFACE - LINE SIDE ELECTRICAL CHARACTERISTIC INFORMATION
51
E3 LINE SIDE PARAMETERS .........................................................................................................................51
FIGURE 8. PULSE MASK FOR E3 (34.368MBPS) INTERFACE AS PER ITU-T G.703 ........................................................................... 51
TABLE 5: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS........................................................ 51
DS3 LINE SIDE PARAMETERS .......................................................................................................................52
FIGURE 9. BELLCORE GR-499-CORE PULSE TEMPLATE REQUIREMENTS FOR DS3 APPLICATIONS.................................................. 52
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 53
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 53
TRANSMIT UTOPIA INTERFACE....................................................................................54
FIGURE 10. TIMING DIAGRAM FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ................................................................................ 54
TABLE 8: TIMING INFORMATION FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ............................................................................. 54
I

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XRT79L72 전자부품, 판매, 대치품
xr
PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
PIN DESCRIPTIONS
PIN #
NAME
TYPE
DESCRIPTION
MICROPROCESSOR INTERFACE
AB26
AC26
AD26
AB25
AA24
AD25
AC25
AB24
AF25
AE25
AF24
AE24
AD24
AC24
AF23
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I Address Bus Input pins Microprocessor Interface:
These input pins permit the Microprocessor to identify on-chip registers and Buffer/
Memory locations (within the XRT79L72 device) whenever it performs READ and
WRITE operations with the XRT79L71 device.
R22 D0 I/O Bi-Directional Data Bus pins Microprocessor Interface:
T24 D1
These pins are used to drive and receive data over the bi-directional data bus.
T25 D2
T26 D3
U22 D4
U23 D5
U24 D6
U25 D7
AB23
ALE/AS
I Address Latch Enable/Address Strobe:
This input pin is used to latch the address present at the Microprocessor Interface
Address Bus pins A[14:0] into the Framer/UNI Microprocessor Interface block and to
indicate the start of a READ or WRITE cycle. This input pin is active high, in the Intel
Mode and active low in the Motorola Mode.
AE23
CS
I Chip Select Input:
The user must assert this active low signal in order to select the Microprocessor
Interface for READ and WRITE operations between the Microprocessor and the UNI/
Framer on-chip registers and RAM locations.
R23 INT O Interrupt Request Output:
This open-drain, active-low output signal will be asserted when the Framer/UNI
device is requesting interrupt service from the Microprocessor. This output pin
should typically be connected to the Interrupt Request input of the Microprocessor.
AD23
RD/DS
I READ Strobe Intel Mode:
If the Microprocessor Interface is operating in the Intel Mode, then this input pin will
function as the RD (READ Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the Framer/UNI will place the contents of the
addressed register within the Framer/UNI IC on the Microprocessor Bi-directional
Data Bus D[7:0]. When this signal is negated, the Data Bus will be tri-stated.
Data Strobe Motorola Mode:
If the Microprocessor Interface is operating in the Motorola Mode, then this input will
function as the DS (Data Strobe) signal.
4

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1-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

Exar Corporation
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XRT79L72

2-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

Exar Corporation
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