PDF XRT82L24A Data sheet ( Hoja de datos )

Número de pieza	XRT82L24A
Descripción	QUAD E1 LINE TRANSCEIVER
Fabricantes	Exar Corporation
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No Preview Available ! áçwww.DataSheet4U.com XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR AUGUST 2004 REV. 1.1.2 GENERAL DESCRIPTION The XRT82L24A is a fully integrated Quad (four chan- nels) short-haul line interface unit for E1(2.048Mbps) 75Ω or 120Ω applications. Each channel consists of a receiver with equalizer for reliable data and clock re- covery, and a transmitter which accepts either single or dual-rail digital inputs for signal transmission to the line using a low output impedance line driver. The de- vice also includes a crystal-less jitter attenuator which, depending on system requirements, can be selected in the receive or transmit path through the Host or Hardware Mode control. XRT82L24A is a low power CMOS device operating on a single 3.3V supply with 5V tolerant digital inputs. FEATURES • Fully integrated quad, short-haul PCM transceivers for E1 applications. • On Chip Receive Equalizer and Transmit Pulse Shaper for CEPT 75Ω and 120Ω line terminations • On chip clock recovery circuit • Transformer or capacitor coupled receiver inputs • Crystal-less jitter attenuator can be selected in the transmit or receive path • High receiver interference immunity • Per-channel transmit power shutdown • Tri-state transmit output capability • On chip per-channel driver failure monitoring circuit • On chip HDB3/B8ZS/AMI encoder/decoder func- tions • Supports Gapped Clock for Multiplexer Mapper Applications • Transmit return loss meets or exceeds ETSI 300 166 standard • Meets or exceeds specifications in ITU G.703, G.775, G.736 and G.823; ETSI 300-166 • Meets or exceeds G.783 and G.823 Jitter Specifi- cations • 3.3V or 5.0V Logic level inputs • Single +3.3V Supply Operation • New Patent# 6,313,671B1 Low Power IC I/O Buffer APPLICATIONS • Digital cross connects (DSX-1) • Channel Banks • High speed data transmission line cards • E1 Multiplexer • Public switching systems and PBX interfaces FIGURE 1. BLOCK DIAGRAM OF THE XRT82L24A E1 LIU (HOST MODE) TxClk_n/RZData_n TxPOS_n/TDATA_n TxNEG_n RxClk_n RxPOS_n/RDATA_n RxNEG_n/LCV_n RxLOS_n INT RDY_DTACK PClk/Codes PTS1/ClkE PTS2/SR_DR Reset ICT HDB3 Encoder MUX Tx/Rx Jitter Attenuator Tx Timing Control Tx Pulse Shaper Line Driver Driver Monitor Enable/ Disable Remote LoopBack Digital LoopBack HDB3 Decoder MUX Channel 0 Channel 1 Channel 2 Channel 3 Tx/Rx Jitter Attenuator LOS Detect Clock Generator Timing & Data Recovery Peak Detector & Slicer Local Analog LoopBack Rx Equalizer Test µP Controller & Hardware Interface TVDD_n TTIP_n TRing_n TGND_n MClk RTIP_n RRing_n ADD [0:3] D[0:7] WR_R/W/TxOFF_0 ALE_AS/TxOFF_2 CS/TxOFF_3 RD_DS/TxOFF_1 HW/HOST Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page áç XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.2 TABLE 3: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ....................................................................... 19 TABLE 4: TRANSMIT PULSE MASK SPECIFICATION ...................................................................................... 19 Figure 14. ITU G.703 E1 Pulse Template .............................................................................................. 20 TABLE 5: DC ELECTRICAL CHARACTERISTICS ............................................................................................ 20 TABLE 6: POWER CONSUMPTION (TA=-40°C TO 85°C, VDD=3.3V + 5%, UNLESS OTHERWISE SPECIFIED.) .. 21 ABSOLUTE MAXIMUM RATINGS ................................................................................... 21 TABLE 7: AC ELECTRICAL CHARACTERISTICS ............................................................................................ 21 Figure 15. Transmit Clock and Input Data Timing .............................................................................. 22 Figure 16. Receive Clock and Output Data Timing. ............................................................................ 22 TABLE 8: MICROPROCESSOR INTERFACE SIGNAL ........................................................................................ 23 TABLE 9: MICROPROCESSOR REGISTER MAP ............................................................................................. 24 TABLE 10: COMMAND CONTROL REGISTER 0 ............................................................................................. 25 TABLE 11: COMMAND CONTROL REGISTER 1 ............................................................................................. 26 TABLE 12: CHANNEL STATUS REGISTER .................................................................................................... 27 TABLE 13: CHANNEL MASK REGISTER ....................................................................................................... 28 TABLE 14: CHANNEL CONTROL REGISTER ................................................................................................ 29 Figure 17. Intel Interface Timing (Read) ............................................................................................... 30 Figure 18. Intel Interface Timing (Write) ............................................................................................... 30 TABLE 15: INTEL INTERFACE TIMING SPECIFICATIONS ................................................................................. 31 Figure 19. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ... 32 Figure 20. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ... 32 Figure 21. Microprocessor Interface Timing - Reset Pulse Width ..................................................... 33 TABLE 16: MOTOROLA INTERFACE TIMING SPECIFICATION .......................................................................... 33 JITTER TOLERANCE .................................................................................................................................... 34 Figure 22. Receive Maximum Jitter Tolerance .................................................................................... 34 Figure 23. Receiver Jitter Transfer Function (Jitter Attenuator disabled) ........................................ 35 Figure 24. Jitter Attenuation Function ................................................................................................. 35 ORDERING INFORMATION ............................................................................................................................ 36 PACKAGE DIMENSIONS 100 LEAD TQFP 14X14MM ..................................................................................... 36 REVISION HISTORY ..................................................................................................................................... 37 II 5 Page áç XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.2 PIN DESCRIPTIONS PIN # 38 46 47 65 79 80 83 88 93 96 97 98 NAME AGND AGND DGND DGND DGND AGND AVDD AVDD AVDD AGND DGND DVDD TYPE DESCRIPTION ** Analog Ground Analog Ground Digital Ground Digital Ground Digital Ground Analog Ground Analog Positive Supply(3.3V± 5%) Analog Positive Supply(3.3V± 5%) Analog Positive Supply(3.3V± 5%) Analog Ground Digital Ground ** Digital Positive Supply(3.3V± 5%) 9 11 Page

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