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XRT83L38 데이터시트 PDF




Exar Corporation에서 제조한 전자 부품 XRT83L38은 전자 산업 및 응용 분야에서
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부품번호 XRT83L38 기능
기능 OCTAL T1/E1/J1 LH/SH TRANSCEIVER
제조업체 Exar Corporation
로고 Exar Corporation 로고


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XRT83L38 데이터시트, 핀배열, 회로
www.DataSheet4U.com
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2004
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83L38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100, E1 (2.048Mbps) 75or
120Ω, or J1 110applications.
In long-haul applications the XRT83L38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83L38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83L38 provides both a parallel Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83L38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75Ω,
100Ω, 110and 120for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1 BLOCK DIAGRAM OF THE XRT83L38 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
MASTER CLOCK SYNTHESIZER
One of Eight channels, CHANNEL_n - (n= 0:7)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TAOS
ENABLE
TIMING
CONTROL
DFM
DRIVE
MONITOR
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
TEST
MICROPROCESSOR CONTROLLER
MCLKOUT
DMO_n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
ICT
µPTS1
µPTS2
D[7:0]
µPCLK
A[7:0]
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT83L38 pdf, 반도체, 판매, 대치품
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 3 PIN OUT OF THE XRT83L38
RNEG_3 / LCV_3
RCLK_3
RLOS_3
TNEG_3 / CODES_3
TPOS_3 / TDATA_3
TCLK_3
TCLK_2
TPOS_2 / TDATA_2
TNEG_2 / CODES_2
DMO_3
JASEL0
JASEL1
TXON_0
TXON_1
TXON_2
TXON_3
A[7] / LOOP1_3
A[6] / LOOP0_3
A[5] / LOOP1_2
A[4] / LOOP0_2
A[3] / LOOP1_1
A[2] / LOOP0_1
A[1] / LOOP1_0
A[0] / LOOP0_0
DVDD PreD river
DVDD Driver
DVDD
DGND
DGND Driver
D GND PreDriver
CLKSEL0
CLKSEL1
CLKSEL2
W R_R/W / EQC0
RD_DS / EQC1
ALE_AS / EQC2
CS / EQC3
RDY_DTACK / EQC4
TAOS_0
TAOS_1
TAOS_2
TAOS_3
DMO_0
TNEG_1 / CODES_1
TPOS_1 / TDATA_1
TCLK_1
TCLK_0
TPOS_0 / TDATA_0
TNEG_0 / CODES_0
RLOS_0
RCLK_0
RNEG_0 / LCV_0
157
158
159
160
161
162
163
164
165
166
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168
169
170
171
172
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175
176
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187
188
189
190
191
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195
196
197
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199
200
201
202
203
204
205
206
207
208
XRT83L38
104 RNEG_7/LCV_7
103 RCLK_7
102 RLOS_7
101 TNEG_7 / CODES_7
100 TPOS_7 / TDATA_7
99 TCLK_7
98 TCLK_6
97 TPOS_6 / TDATA_6
96 TNEG_6 / CODES_6
95 DMO_7
94 µPCLK / ATAOS
93 TXON_7
92 TXON_6
91 TXON_5
90 TXON_4
89 RXMUTE
88 ICT
87 TEST
86 TERSEL0
85 TERSEL1
84 TXTSEL
83 RXTSEL
82 RXRES0
81 RXRES1
80 HW _HOST
79 DVDD
78 DVDD
77 DGND
76 DGND
75 RESET
74 D[0] / LOOP0_7
73 D[1] / LOOP1_7
72 D[2] / LOOP0_6
71 D[3] / LOOP1_6
70 D[4] / LOOP0_5
69 D[5] / LOOP1_5
68 D[6] / LOOP0_4
67 D[7] / LOOP1_4
66 TAOS_7
65 TAOS_6
64 TAOS_5
63 TAOS_4
62 DMO_4
61 TNEG_5 / CODES_5
60 TPOS_5 / TDATA_5
59 TCLK_5
58 TCLK_4
57 TPOS_4 / TDATA_4
56 TNEG_4 / CODES_4
55 RLOS_4
54 RCLK_4
53 RNEG_4 / LCV_4
4

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XRT83L38 전자부품, 판매, 대치품
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
Internal Receive Termination Mode.........................................................................................................31
TABLE 6: RECEIVE TERMINATION CONTROL .............................................................................................................. 32
FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE ........................... 32
TABLE 7: RECEIVE TERMINATIONS ............................................................................................................................ 32
FIGURE 14. SIMPLIFIED DIAGRAM FOR T1 IN THE EXTERNAL TERMINATION MODE (RXTSEL= 0)................................ 33
TRANSMITTER (CHANNELS 0 - 7) .............................................................................................. 34
Transmit Termination Mode.....................................................................................................................34
External Transmit Termination Mode ......................................................................................................34
FIGURE 15. SIMPLIFIED DIAGRAM FOR E1 IN EXTERNAL TERMINATION MODE (RXTSEL= 0) ...................................... 34
TABLE 8: TRANSMIT TERMINATION CONTROL ............................................................................................................ 34
TABLE 9: TERMINATION SELECT CONTROL................................................................................................................ 34
REDUNDANCY APPLICATIONS............................................................................................... 35
TABLE 10: TRANSMIT TERMINATION CONTROL .......................................................................................................... 35
TABLE 11: TRANSMIT TERMINATIONS ........................................................................................................................ 35
TYPICAL REDUNDANCY SCHEMES ....................................................................................... 36
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT SECTION FOR 1:1 & 1+1 REDUNDANCY .......................... 37
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR 1:1 AND 1+1 REDUNDANCY .................................. 37
FIGURE 18. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY............................................. 38
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR N+1 REDUNDANCY............................................... 39
PATTERN TRANSMIT AND DETECT FUNCTION................................................................................. 40
TRANSMIT ALL ONES (TAOS)....................................................................................................... 40
NETWORK LOOP CODE DETECTION AND TRANSMISSION ................................................................ 40
TABLE 12: PATTERN TRANSMISSION CONTROL .......................................................................................................... 40
TABLE 13: LOOP-CODE DETECTION CONTROL .......................................................................................................... 40
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)........................................... 41
LOOP-BACK MODES ..................................................................................................................... 42
LOCAL ANALOG LOOP-BACK (ALOOP) ......................................................................................... 42
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE .............................................................................................. 42
TABLE 15: LOOP-BACK CONTROL IN HOST MODE....................................................................................................... 42
FIGURE 20. LOCAL ANALOG LOOP-BACK SIGNAL FLOW .............................................................................................. 42
REMOTE LOOP-BACK (RLOOP).................................................................................................... 43
FIGURE 21. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH.................................. 43
FIGURE 22. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH ............................... 43
DIGITAL LOOP-BACK (DLOOP)..................................................................................................... 44
DUAL LOOP-BACK ........................................................................................................................ 44
FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH ................................ 44
FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE ............................................................................................... 44
MICROPROCESSOR PARALLEL INTERFACE..............................................................45
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ................................................................................ 45
MICROPROCESSOR REGISTER TABLES .......................................................................................... 46
TABLE 17: MICROPROCESSOR REGISTER ADDRESS .................................................................................................. 46
TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION ...................................................................................... 46
MICROPROCESSOR REGISTER DESCRIPTIONS ............................................................................... 50
TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ................................................................................ 50
TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ................................................................................ 51
TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ................................................................................ 53
TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ................................................................................ 55
TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ................................................................................ 57
TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ................................................................................ 58
TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ................................................................................ 60
TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ................................................................................ 61
TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ................................................................................ 62
TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ................................................................................ 62
TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION .............................................................................. 63
TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION .............................................................................. 63
TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION .............................................................................. 64
II

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