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PDF XRT83VSH316 Data sheet ( Hoja de datos )
| Número de pieza | XRT83VSH316 | |
| Descripción | 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT83VSH316
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
JULY 2007
REV. P1.0.3
GENERAL DESCRIPTION
The XRT83VSH316 is a fully integrated 16-channel
short-haul line interface unit (LIU) that operates from
a 1.8V Inner Core and 3.3V I/O power supplies.
Using internal termination, the LIU provides one bill of
materials to operate in T1, E1, or J1 mode
independently on a per channel basis with minimum
external components. The LIU features are
programmed through a standard parallel
microprocessor interface or SPI (Serial Mode).
EXAR’s LIU has patented high impedance circuits
that allow the transmitter outputs and receiver inputs
to be high impedance when experiencing a power
failure or when the LIU is powered off. Key design
features within the LIU optimize 1:1 or 1+1
redundancy and non-intrusive monitoring applications
to ensure reliability without using relays.
The on-chip clock synthesizer generates T1/E1/J1
clock rates from a selectable external clock frequency
and has five output clock references that can be used
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH316
for external timing (8kHz, 1.544Mhz, 2.048Mhz,
nxT1/J1, nxE1).
Additional features include System Side LOS, AIS,
QRSS/PRBS and Line Side RLOS, AIS, QRSS/
PRBS, DMO with 16-bit LCV counters and diagnostic
loopback modes for each channel.
APPLICATIONS
• T1 Digital Cross Connects (DSX-1)
• ISDN Primary Rate Interface
• CSU/DSU E1/T1/J1 Interface
• T1/E1/J1 LAN/WAN Routers
• Public Switching Systems and PBX Interfaces
• T1/E1/J1 Multiplexer and Channel Banks
• Integrated Multi-Service Access Platforms (IMAPs)
• Integrated Access Devices (IADs)
• Inverse Multiplexing for ATM (IMA)
• Wireless Base Stations
RCLK
RPOS
RNEG/LCV
TCLK
TPOS
TNEG
SLOS
Channel N of 16
B8ZS/HDB3
Decoder
32-bit/64-bit
Jitter Attenuator
Clock & Data
Recovery (CDR)
Peak Detector
& Slicer
System Generator
SAIS, SLOS, SPRBS
Line Detector
AIS, RLOS, PRBS,
LCV
MUX
Line Generator
PRBS
System Detector
SAIS, SLOS, SPRBS
Digital
Loop Back
Remote
Loop Back
Analog
Loop Back
DMO
B8ZS/HDB3
Encoder
32-bit/64-bit
Jitter Attenuator
Timing
Control
Tx Pulse Shaper
Line Driver
AIS
RTIP
RRING
RLOS
RxON
RxTSEL
DMO
TTIP
TRING
TxON
JTAG
Test
Parallel
Microprocessor
SPI
Microprocessor
PLL
MCLKnOUT
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
PRELIMINARY
XRT83VSH316
REV. P1.0.3
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 37
FIGURE 22. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 37
5.0 T1/E1 APPLICATIONS ........................................................................................................................ 38
5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 38
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 38
FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 38
5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 39
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK.................................................................................................... 39
5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 40
FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 40
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 41
FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ........................................................................................................ 41
5.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 42
FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ..................................................................................... 42
5.3 LINE CARD REDUNDANCY .......................................................................................................................... 43
5.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 43
5.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 43
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 43
5.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 44
FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 44
5.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 44
5.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 45
FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY...................................................... 45
5.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 46
FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY........................................................ 46
5.4 POWER FAILURE PROTECTION .................................................................................................................. 47
5.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 47
5.6 NON-INTRUSIVE MONITORING .................................................................................................................... 47
FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION .............................................................. 47
5.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 48
FIGURE 33. ATP TESTING BLOCK DIAGRAM..................................................................................................................................... 48
FIGURE 34. TIMING DIAGRAM FOR ATP TESTING ........................................................................................................................... 48
5.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 48
6.0 MICROPROCESSOR INTERFACE ..................................................................................................... 49
6.1 SPI SERIAL PERIPHERAL INTERFACE BLOCK ......................................................................................... 49
FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 49
6.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 49
FIGURE 36. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 49
6.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 50
6.1.3 ADDR[9:0] (SCLK1 - SCLK10)................................................................................................................................... 50
6.1.4 R/W (SCLK11)............................................................................................................................................................. 50
6.1.5 DUMMY BITS (SCLK12 - SCLK16) ............................................................................................................................ 50
6.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 50
6.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 50
FIGURE 37. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 51
6.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 52
FIGURE 38. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK.................................................................. 52
6.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 53
6.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .............................................................. 55
FIGURE 39. INTEL µP INTERFACE TIMING DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WHEN ALE IS NOT TIED ’HIGH’56
FIGURE 40. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WITH ALE=HIGH ................. 57
6.5 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 58
FIGURE 41. MOTOROLA MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................... 59
FIGURE 42. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................ 60
7.0 REGISTER DESCRIPTIONS ............................................................................................................... 61
7.1 GLOBAL CONFIGURATION REGISTERS (0X000 - 0X00F) ......................................................................... 62
7.2 CHANNEL CONTROL REGISTERS (LINE AND SYSTEM SIDE) ................................................................. 63
7.3 OFFSET FOR PROGRAMMING THE CHANNEL NUMBER, N .................................................................... 63
7.4 GLOBAL CONTROL REGISTERS ................................................................................................................. 64
FIGURE 43. REGISTER 0X0009H SUB REGISTERS........................................................................................................................... 69
7.5 CONTROL AND LINE SIDE DIAGNOSTIC REGISTERS .............................................................................. 74
7.6 SYSTEM SIDE DIAGNOSTIC CHANNEL CONTROL REGISTERS .............................................................. 85
8.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 89
II
5 Page 
REV. P1.0.3
RECEIVER SECTION
NAME
RPOS15
RPOS14
RPOS13
RPOS12
RPOS11
RPOS10
RPOS9
RPOS8
RPOS7
RPOS6
RPOS5
RPOS4
RPOS3
RPOS2
RPOS1
RPOS0
PIN
U12
U19
P19
W15
B15
G19
D19
D12
D9
D2
G2
B6
W6
P2
U2
U9
RNEG15
RNEG14
RNEG13
RNEG12
RNEG11
RNEG10
RNEG9
RNEG8
RNEG7
RNEG6
RNEG5
RNEG4
RNEG3
RNEG2
RNEG1
RNEG0
W11
T18
P18
N19
H19
G18
E18
B11
B10
E3
G3
H2
N2
P3
T3
W10
PRELIMINARY
XRT83VSH316
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TYPE
O
DESCRIPTION
RPOS/RDATA Output
Receive digital output pin. In dual rail mode, this pin is the receive positive
data output. In single rail mode, this pin is the receive non-return to zero (NRZ)
data output.
O RNEG/LCV_OF Output
In dual rail mode, this pin is the receive negative data output. In single rail
mode, this pin can either be a Line Code Violation or Overflow indicator. If LCV
is selected by software and if a line code violation, a bi-polar violation, or
excessive zeros occur, the LCV pin will pull "High" for a minimum of one RCLK
cycle. LCV will remain "High" until there are no more violations. However, if
OF is selected the LCV pin will pull "High" if the internal LCV counter is satu-
rated. The LCV pin will remain "High" until the LCV counter is reset.
9
11 Page | ||
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| PDF Descargar | [ Datasheet XRT83VSH316.PDF ] | |
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