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6225CA 데이터시트, 핀배열, 회로
www.DataSheet4U.com ®
Data Sheet
September 2003
ISL6225
FN9049.4
Dual Mobile-Friendly PWM Controller with
DDR Memory Option
The ISL6225 dual PWM controller delivers high efficiency and
tight regulation from two voltage regulating synchronous buck
DC/DC converters. The ISL6225 PWM power supply controller
was designed especially for DDR DRAM, SDRAM, and graphic
chipset applications in high performance desknote PCs,
notebook PCs, sub-notebook PCs, and PDAs.
Automatic mode selection of constant-frequency synchronous
rectification at heavy load, and hysteretic diode-emulation at
light load, assure high efficiency over a wide range of
conditions. The hysteretic mode of operation can be disabled
separately on each PWM converter if constant-frequency
continuous-conduction operation is desired for all load levels.
Efficiency is further enhanced by using the lower MOSFET
RDS(ON) as the current sense element.
Voltage-feed-forward ramp modulation, average current mode
control, and internal feedback compensation provide fast
response to input voltage and output load transients. Input
current ripple is minimized by channel to channel PWM
phase shift of 0°, 90°, or 180° determined by input voltage
and status of the DDR pin.
The ISL6225 can control two independent output voltages
adjustable from 0.9V to 5.5V or, by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory
systems. The reference voltage VREF required by DDR
memory is generated as well.
In dual power supply applications the ISL6225 monitors the
output voltage of both CH1 and CH2. An independent
PGOOD (power good) signal is asserted for each channel
after the soft-start sequence has completed, and the output
voltage is within ±10% of the set point. In DDR mode CH1
generates the only PGOOD signal.
Built-in over-voltage protection prevents the output from
going above 115% of the set point by holding the lower
MOSFET on and the upper MOSFET off. When the output
voltage decays below the over-voltage threshold, normal
operation automatically resumes. Once the soft-start
sequence has completed, under-voltage protection may
latch the ISL6225 off if either output drops below 75% of its
set point value.
Adjustable over-current protection (OCP) monitors the
voltage drop across the RDS(ON) of the lower MOSFET. If
more precise current-sensing is required, an external current
sense resistor may be used.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
PKG. NO.
ISL6225CA
-10 to 85
28 Ld SSOP
M28.15
ISL6225CA-T
-10 to 85 28 Ld SSOP Tape
and Reel
M28.15
Features
• Provides regulated output voltage in the range of 0.9V-5.5V
- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at
light load
- Inhibit Hysteretic mode on one, or both channels
• Complete DDR memory power solution
- VTT tracks VDDQ/2
- VDDQ/2 buffered reference output
• No current-sense resistor required
- Uses MOSFET RDS(ON)
- Optional current-sense resistor for precision Over-Current
• Under-voltage lock-out on VCC pin
• Dual input voltage mode operation
- Operates directly from battery 5V to 24V input
- Operates from 3.3V or 5V system rail
- VCC from 5V only
• Excellent dynamic response
- Combined voltage feed-forward and average current
mode control
• Power-good signal for each channel
• 300kHz switching frequency
- 180° channel to channel phase operation for reduced input
ripple when not in DDR mode
- 0° channel to channel phase operation in DDR mode for
reduced channel interference
- 90° channel to channel phase operation for reduced input
ripple in DDR mode when VIN is at GND.
Applications
Mobile PCs
• PDAs
• Hand-held portable instruments
Pinout
ISL6225
SSOP-28
TOP VIEW
GND 1
28 VCC
LGATE1 2
27 LGATE2
PGND1 3
26 PGND2
PHASE1 4
25 PHASE2
UGATE1 5
24 UGATE2
BOOT1 6
23 BOOT2
ISEN1 7
22 ISEN2
EN1 8
21 EN2
VOUT1 9
20 VOUT2
VSEN1 10
19 VSEN2
OCSET1 11
18 OCSET2
SOFT1 12
17 SOFT2
DDR 13
16 PG2/REF
VIN 14
15 PG1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




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ISL6225
Functional Pin Description
GND (Pin 1)
Signal ground for the IC.
LGATE1, LGATE2 (Pin 2, 27)
These are outputs of the lower MOSFET drivers.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers. These pins are connected to sources of the lower
MOSFETs of their respective converters.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
These pins provide the gate drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect this pin to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. Anode of
the bootstrap diode is connected to the VCC pin.
ISEN1, ISEN2 (Pin 7, 22)
These pins are used to monitor the voltage drop across the
lower MOSFET for current feedback and Over-Current
protection. For precise current detection these inputs can be
connected to the optional current sense resistors placed in
series with the source of the lower MOSFETs.
EN1, EN2 (Pin 8, 21)
These pins enable operation of the respective converter
when high. When both pins are low, the chip is disabled and
only low leakage current <1µA is taken from VCC and VIN.
These pins are to be connected together and switched at the
same time.
VOUT1, VOUT2 (Pin 9, 20)
These pins when connected to the converters’ respective
outputs provide the output voltage inside the chip to reduce
output voltage excursion during HYS/PWM transition. When
connected to ground, these pins command forced
converters operate in continuous conduction mode at all
load levels.
VSEN1, VSEN2 (Pin 10, 19)
These pins are connected to the resistive dividers that set
the desired output voltage. The PGOOD, UVP, and OVP
circuits use this signal to report output voltage status.
OCSET1 (Pin 11)
A resistor from this pin to ground sets the over current
threshold for the first controller.
SOFT1, SOFT2 (Pin 12, 17)
These pins provide soft-start function for their respective
controllers. When the chip is enabled, the regulated 5µA
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SOFT pin.
DDR (Pin 13)
This pin, when high, transforms dual channel chip into
complete DDR memory solution. The OCSET2 pin becomes
an input to provide the required tracking function. The
channel synchronization is changed from out-of-phase to in-
phase. The PG2/REF pin becomes the output of the VDDQ/
2 buffered voltage that is used as a reference voltage by the
second channel.
VIN (Pin 14)
Provides battery voltage to the oscillator for feed-forward
rejection of the input voltage variation.
When connected to ground via 100kresistor while the
DDR pin is high, this pin commands the out-of-phase 90o
channels synchronization for reduces inter-channel
interference.
PG1 (Pin 15)
PGOOD1 is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the first
channel output is not within ±10% of the set value.
PG2/REF (Pin 16)
This pin has a double function depending on the mode the
chip is operating. When the chip is used as a dual channel
PWM controller (DDR=0), the pin provides a PGOOD2
function for the second channel. The pin is pulled low when
the second channel output is not within ±10% of the set value.
In DDR mode (DDR=1), this pin serves as an output of the
buffer amplifier that provides VDDQ/2 reference voltage
applied to the OCSET2 pin.
OCSET2 (Pin 18)
In a dual channel application (DDR=0), a resistor from this
pin to ground sets the over current threshold for the second
controller.
In the DDR application (DDR=1), this pin sets the output
voltage of the buffer amplifier and the second controller and
should be connected to the center point of a divider from the
VDDQ output.
VCC (Pin 28)
This pin powers the controller.
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ISL6225
Description
Operation
The ISL6225 is a dual channel PWM controller intended for
use in power supplies for graphic chipset, SDRAM, DDR
DRAM or other low voltage power applications in modern
notebook and sub-notebook PCs. The IC integrates two
control circuits for two synchronous buck converters. The
output voltage of each controller can be set in the range of
0.9V to 5.5V by an external resistive divider. Out-of-phase
operation with 180 degree phase shift reduces input current
ripple.
The synchronous buck converters can operate from either
an unregulated DC source such as a notebook battery with a
voltage ranging from 5.0V to 24V, or from a regulated
system rail of 3.3V or 5V. In either mode of operation the
controller is biased from the +5V source.
The controllers operate in the current mode with input
voltage feed-forward for simplified feedback loop
compensation and reduced effect of the input voltage
variation. An integrated feedback loop compensation
dramatically reduces the number of external components.
Depending on the load level, converters can operate either
in a fixed-frequency mode or in a hysteretic mode. Switch-
over to the hysteretic mode operation at light loads improves
the converters' efficiency and prolongs battery run time. The
hysteretic mode of operation can be inhibited independently
for each channel if a variable frequency operation is not
desired.
The ISL6225 has a special means to rearrange its internal
architecture into a complete DDR solution. When DDR input
is set high, the second channel can provide the capability to
track the output voltage of the first channel. The buffered
reference voltage required by DDR memory chips is also
provided.
Initialization
The Power-On Reset (POR) function continually monitors
the bias supply voltage on the VCC pin and initiates soft-start
operation after the input supply voltage exceeds 4.5V.
Should this voltage drop lower than 4.0V, the POR disables
the chip.
Soft-Start
When soft start is initiated, the voltage on the SOFT pin
starts to ramp gradually due to the 5µA current sourced into
the external soft-start capacitor. The output voltage starts to
follow the soft-start voltage.
When the SOFT pin voltage reaches a level of 0.9V, the
output voltage comes into regulation while the soft-start pin
voltage continues to rise. When the SOFT voltage reaches
1.5V, the power good (PGOOD), the mode control, and the
fault functions are enabled, as depicted in Figure 3.
EN
1
1.5V
0.9V
SOFT
2
VOUT
3
PGOOD
4
Ch1 5.0V
Ch3 1.0V
Ch2 2.0V
Ch4 5.0V
FIGURE 3. START UP
M1.00ms
This completes the soft start sequence. Further rise of pin
voltage does not affect the output voltage. During the soft-
start, the converter always operates in continuous
conduction mode independently of the load level or FCCM
pin potential.
The soft-start time (the time from the moment when EN
becomes high to the moment when PGOOD is reported) is
determined by the following equation.
TSOFT = -1---.-5----V--5---×-µ---C-A----s---o---f--t
The time it takes the output voltage to come into regulation
can be obtained from the following equation.
TRISE = 0.6 × TSOFT
Having such a spread between the time when the output
voltage reaches the regulation point and the moment when
PGOOD is reported allows for a fault-safe test mode by
means of an external circuit that clamps the SOFT pin
voltage on the level 0.9V<VSOFT<1.5V.
Output Voltage Program
The output voltage of either channel is set by a resistive divider
from the output to ground. The center point of the divider is
connected to VSEN pin as shown in Figure 4. The output
voltage value is determined by the following equation.
VO = -0---.-9---V----------(R--R---2-1-----+-----R----2----)
Where 0.9V is the value of the internal reference. The VSEN
pin voltage is also used by the controller for the power good
function and to detect Under-Voltage and Over-Voltage
conditions.
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6225CA

ISL6225CA

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