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PDF XRT91L30 Data sheet ( Hoja de datos )
| Número de pieza | XRT91L30 | |
| Descripción | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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PRELIMINARY
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
JANUARY 2006
GENERAL DESCRIPTION
The XRT91L30 is a fully integrated SONET/SDH
transceiver for SONET/SDH 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 applications.
The transceiver includes an on-chip Clock Multiplier
Unit (CMU), which uses a high frequency Phase-
Locked Loop (PLL) to generate the high-speed
transmit serial clock from a slower external clock
reference. It also provides Clock and Data Recovery
(CDR) function by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial
data stream. The internal CDR unit can be disabled
and bypassed in lieu of an externally recovered
received clock from the optical module. Either the
internally recovered clock or the externally recovered
clock can be used for loop timing applications. The
chip provides serial-to-parallel and parallel-to-serial
converters using an 8-bit wide LVTTL system
interface in both receive and transmit directions.
The transmit section includes an option to accept a
REV. P1.0.8
parallel clock signal from the framer/mapper to
synchronize the transmit section timing. The device
can internally monitor Loss of Signal (LOS) condition
and automatically mute received data upon LOS. An
on-chip SONET/SDH frame byte and boundary
detector and frame pulse generator offers the ability
recover SONET/SDH framing and to byte align the
receive serial data stream into the 8-bit parallel bus.
APPLICATIONS
• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment
FIGURE 1. BLOCK DIAGRAM OF XRT91L30
TXDI[7:0]
8
TXPCLK_IO
REFCLKP/N
TTLREFCLK
CDRAUXREFCLK
RXDO[7:0]
RXPCLKO
ENB
ENB
WP
RP
Div by
8
STS-12/STM-4 or STS-3/STM-1
TRANSCEIVER
PISO
(Parallel Input
Serial Output)
DLOOP
Re-Timer
CMU
RLOOPS
SIPO
(Serial Input
Parallel Output)
8
Div by 8
CDR
Loop Filters
Control Block
ALOOP
TXOP/N
RXIP/N
XRXCLKIP/N
Clock Control
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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PRELIMINARY
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30
REV. P1.0.8
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 25
FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 25
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 26
TABLE 14: CLOCK MULTIPLIER UNIT PERFORMANCE ....................................................................................................................... 26
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 27
TABLE 15: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS ................................................................................................. 27
FIGURE 16. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK ....................................................... 28
3.8 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 28
FIGURE 17. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 28
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 29
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 29
FIGURE 18. SERIAL REMOTE LOOPBACK......................................................................................................................................... 29
4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 29
FIGURE 19. DIGITAL LOCAL LOOPBACK........................................................................................................................................... 29
4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 30
FIGURE 20. ANALOG LOCAL LOOPBACK .......................................................................................................................................... 30
4.4 SPLIT LOOPBACK ......................................................................................................................................... 30
FIGURE 21. SPLIT LOOPBACK......................................................................................................................................................... 30
4.5 EYE DIAGRAM ............................................................................................................................................... 31
FIGURE 22. TRANSMIT ELECTRICAL OUTPUT EYE DIAGRAM............................................................................................................. 31
4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 31
4.6.1 JITTER TOLERANCE: ................................................................................................................................................ 31
FIGURE 23. GR-253 JITTER TOLERANCE MASK .............................................................................................................................. 32
FIGURE 24. XRT91L30 MEASURED JITTER TOLERANCE ................................................................................................................. 32
4.6.2 JITTER GENERATION................................................................................................................................................ 33
FIGURE 25. XRT91L30 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 622.08 MBPS STS-12/STM4 USING
’1010’ OUTPUT PATTERN................................................................................................................................................. 33
5.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 34
ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 34
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ......................................................... 34
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 34
................................................................................................................................................................... 34
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS...................................... 35
ORDERING INFORMATION .................................................................................................................. 36
PACKAGE DIMENSIONS ................................................................................................ 36
REVISION HISTORY ...................................................................................................................................... 37
II
5 Page 
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REV. P1.0.8
RECEIVER SECTION
NAME
RXDO0
RXDO1
RXDO2
RXDO3
RXDO4
RXDO5
RXDO6
RXDO7
RXIP
RXIN
LEVEL
LVTTL
TYPE
O
Diff LVPECL
I
XRXCLKIP
XRXCLKIN
Diff LVPECL
I
RXPCLKO
LVTTL
O
CDRAUX-
REFCLK
LVTTL
I
OOF
LVTTL
I
FRAMEPULSE
LVTTL
O
PRELIMINARY
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
PIN DESCRIPTION
19 Receive Parallel Data Output
20 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
22 8-bit parallel receive data output is updated simultaneously on
23 the rising edge of the RXPCLKO output. The 8-bit parallel
interface is de-multiplexed from the receive serial data input
24 MSB first (RXDO[7:0]). The XRT91L30 will output the data on
25 the falling edge of this clock.
26
27
13 Receive Serial Data Input
14 The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is applied to
these input pins.
8 External Recovered Receive Clock Input
9 The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is sampled on
the rising edge of this externally recovered differential clock
coming from the optical module. It is used when the internal
CDR unit is disabled and bypassed by the CDRDIS pin.
NOTE: In the event that XRXCLKIP/N differential input pins are
unused, XRXCLKIP should be tied to VCC with a 1k
Ohm pull-up and XRXCLKIN should be tied to Ground
with a 1k Ohm pull-down.
29 Receive Parallel Clock Output (77.76 MHz or 19.44 MHz)
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
clock output reference for the 8-bit parallel receive data output
RXDO[7:0]. The parallel received data output bus will be
updated on the falling edge of this clock.
32 Clock and Data Recovery Auxillary Reference Clock
77.76 MHz ± 500 ppm auxillary reference clock for the CDR.
NOTE: In the event that CDRAUXREFCLK LVTTL input pin is
unused, CDRAUXREFCLK should be tied to ground.
11 Out of Frame Input Indicator
This level sensitive input pin is used to initiate frame detection
and byte alignment recovery when OOF is declared by the
downstream device. When this pin is held High, FRAME-
PULSE will pulse for a single RXPCLKO period upon the detec-
tion of every third frame alignment A2 byte in the incoming
SONET/SDH Frame.
"Low" = Normal Operation
"High" = OOF Indication initiating frame detection and byte
boundary recovery and activating FRAMEPULSE
30 Sonet Frame Alignment Pulse
This pin will generate a single pulse for an RXPCLKO clock
period upon the detection of the third frame alignment A2 byte
whenever the OOF input pin is held High. The parallel received
data output bus will then be byte aligned to this newly recov-
ered SONET/SDH frame.
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT91L30.PDF ] | |
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