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PDF XRT91L80 Data sheet ( Hoja de datos )
| Número de pieza | XRT91L80 | |
| Descripción | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
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XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
JANUARY 2007
GENERAL DESCRIPTION
The XRT91L80 is a fully integrated SONET/SDH
transceiver for SONET OC-48/STM-16 applications
supporting the use of Forward Error Correction (FEC)
capability. The transceiver includes an on-chip Clock
Multiplier Unit (CMU), which uses a high frequency
Phase-Locked Loop (PLL) to generate the high-
speed transmit serial clock from a slower external
clock reference. It also provides Clock and Data
Recovery (CDR) functions by synchronizing its on-
chip Voltage Controlled Oscillator (VCO) to the
incoming serial data stream. The chip provides serial-
to-parallel and parallel-to-serial converters and 4-bit
LVDS system interfaces in both receive and transmit
directions. The transmit section includes a 4x9 Elastic
Buffer (FIFO) to absorb any phase differences
between the transmitter clock input and the internally
generated transmitter reference clock. In the event of
an overflow, an internal FIFO control circuit outputs
an OVERFLOW indication. The FIFO under the
REV. 1.0.0
control of the FIFO_AUTORST pin can automatically
recover from an overflow condition. The operation of
the device can be monitored by checking the status of
the LOCKDET_CMU, LOCKDET_CDR, and
LOSDET output signals. An on-chip phase/frequency
detector and charge-pump offers the ability to form a
de-jittering PLL with an external VCXO that can be
used in loop timing mode to clean up the recovered
clock in the receive section.
APPLICATIONS
• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches and Routers
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment
FIGURE 1. BLOCK DIAGRAM OF XRT91L80
FIFO_RST
FIFO_AUTORST
TXDI0P/N
TXDI1P/N
TXDI2P/N
TXDI3P/N
TXPCLKIP/N
TXPCLKOP/N
TXCLKO16P/N
TXCLKO16DIS
RXDO0P/N
RXDO1P/N
RXDO2P/N
RXDO3P/N
RXPCLKOP/N
RXCLKO16P/N
DISRD
STS-48 TRANSCEIVER
WP
RP
RLOOPP
Div by 4
Div by 16
PISO
(Parallel Input
Serial Output)
Re-Timer
CMU
DLOOP RLOOPS
Div by 4
Div by 16
SIPO
(Serial Input
Parallel Output)
CDR
TDO
TDI
TCK
TMS
TRST
JTAG
Serial
Microprocessor
Hardware
Control
TXOP/N
PFD
& Charge Pump
RXIP/N
LOSDMUTE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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REV. 1.0.0
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
FIGURE 14. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER .................................................................................................. 23
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 23
FIGURE 15. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 23
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 24
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 24
FIGURE 16. SERIAL REMOTE LOOPBACK......................................................................................................................................... 24
4.2 PARALLEL REMOTE LOOPBACK ............................................................................................................... 24
FIGURE 17. PARALLEL REMOTE LOOPBACK .................................................................................................................................... 24
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 25
FIGURE 18. DIGITAL LOOPBACK...................................................................................................................................................... 25
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 26
4.4.1 JITTER TOLERANCE: ................................................................................................................................................ 26
FIGURE 19. JITTER TOLERANCE MASK............................................................................................................................................ 26
FIGURE 20. 91L80 MEASURED JITTER TOLERANCE WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT 2.488 GBPS IN STS-
48.................................................................................................................................................................................. 27
4.4.2 JITTER TRANSFER .................................................................................................................................................... 27
FIGURE 21. 91L80 MEASURED JITTER TRANSFER WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT 2.488 GBPS IN STS-
48.................................................................................................................................................................................. 27
4.4.3 JITTER GENERATION................................................................................................................................................ 28
FIGURE 22. 91L80 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.488 GBPS...................................... 28
FIGURE 23. 91L80 MEASURED ELECTRICAL PHASE NOISE RECEIVE JITTER GENERATION AT 2.488 GBPS........................................ 28
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ......................................................................... 29
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 29
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 29
FIGURE 25. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 29
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 30
5.2.1 R/W (SCLK1)............................................................................................................................................................... 30
5.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 30
5.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 30
5.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 30
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 30
6.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 31
TABLE 10: MICROPROCESSOR REGISTER MAP................................................................................................................................ 31
TABLE 11: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................. 31
TABLE 12: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................. 32
TABLE 13: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................. 32
TABLE 14: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................. 33
TABLE 15: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ................................................................................................. 35
TABLE 16: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION ................................................................................................. 35
TABLE 17: MICROPROCESSOR REGISTER 0X3EH BIT DESCRIPTION ................................................................................................. 37
TABLE 18: MICROPROCESSOR REGISTER 0X3FH BIT DESCRIPTION ................................................................................................. 37
7.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 38
ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 38
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 38
................................................................................................................................................................... 39
COMMON MODE LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ................................................ 39
................................................................................................................................................................... 39
LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS .......................................................... 39
LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS............................................................... 40
LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS ........................................................... 40
ORDERING INFORMATION .................................................................................................................. 41
REVISION HISTORY ...................................................................................................................................... 42
II
5 Page 
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REV. 1.0.0
RECEIVER SECTION
NAME
LEVEL
RXDO0P
RXDO0N
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
LVDS
RXPCLKOP
RXPCLKON
LVDS
DISRD
LVTTL
LVCMOS
RXIP
RXIN
CMLDIFF
XRES1P
XRES1N
-
RXCLKO16P
RXCLKO16N
LVDS
LOCKDET_CDR LVCMOS
SDEXT
LVTTL,
LVCMOS
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TYPE
O
O
I
I
I
O
O
I
PIN DESCRIPTION
E13 Receive Parallel Data Output
F13 622Mbps 4-bit parallel receive data output is updated simulta-
C14 neously on the rising edge of the RXPCLKOP/N output. The 4-
D14 bit parallel interface is de-multiplexed from the receive serial
C13 data input MSB first (RXDO3P/N).
D13 NOTE: The XRT91L80 can output 666.51 Mbps 4-bit parallel
receive data output for Forward Error Correction (FEC)
A14 Applications.
B14
E14 Receive Parallel Clock Output
F14 622.08 MHz parallel clock output used to update the 4-bit paral-
lel receive data output RXDO[3:0]P/N at the rising edge of this
clock..
NOTE: The XRT91L80 can output a 666.51 MHz receive clock
output for Forward Error Correction (FEC).
C12 Parallel Receive Data Output Disable
This pin is used to disable the RXDO[3:0]P/N parallel receive
data output bus asynchronously.
"Low" = Normal Mode
"High" = Forces RXDO[3:0]P/N to a logic state "0"
This pin is provided with an internal pull-down.
C1 Receive Serial Data Input
D1 The receive serial data stream of 2.488 Gbps is applied to
these input pins. In Forward Error Correction, the receive
serial data stream is 2.666 Gbps.
G1 External LVDS Biasing Resistors
F1 A 402Ω resistor with +/-1% tolerance should be placed across
these 2 pins for proper biasing.
A6 Auxiliary Clock Output (155.52/166.63 MHz)
A7 155.52/166.63 MHz auxiliary clock derived from divide-by-16
CDR recovered clock.
C7 CDR Lock Detect
This pin is used to monitor the lock condition of the clock and
data recovery unit.
"Low" = CDR Out of Lock
"High" = CDR Locked
B5 Signal Detect Input from Optical Module
Hardware Mode When inactive, it will immediately declare a
Loss of Signal Detect (LOSD) condition and assert LOSDET
output pin and control the activity of the RXDO[3:0]P/N parallel
data output based on LOSDMUTE pin setting.
Host Mode In addition to asserting LOSDET output pin, it will
update the LOSD condition on the registers and control the
activity of the RXDO[3:0]P/N parallel data output based on
LOSDMUTE register bit setting.
"Active" = Normal Operation
"Inactive" = LOSD Condition (SDEXT detects signal absence)
This pin is provided with an internal pull-down.
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT91L80.PDF ] | |
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