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부품번호 XRT72L52 기능
기능 TWO CHANNEL DS3/E3 FRAMER IC
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XRT72L52 데이터시트, 핀배열, 회로
áçwww.DataSheet4U.com
PRELIMINARY
XRT72L52
JANUARY 2001
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
GENERAL DESCRIPTION
The XRT72L52, 2 Channel DS3/E3 Framer IC is de-
signed to accept “User Data” from the Terminal
Equipment and insert this data into the “payload” bit-
fields within an “outbound” DS3/E3 Data Stream. Fur-
ther, the Framer IC is also designed to receive an “in-
bound” DS3/E3 Data Stream (from the Remote Ter-
minal Equipment) and extract out the “User Data”.
The XRT72L52 DS3/E3 Framer device is designed to
support full-duplex data flow between Terminal Equip-
ment and an LIU (Line Interface Unit) IC. The Framer
Device will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 Framing Formats.
The XRT72L52 DS3/E3 Framer IC consists of two
Transmit sections, two Receiver sections, two Perfor-
mance Monitor Sections and a Microprocessor inter-
face.
The Transmit Sections, include a Transmit Payload
Data Input Interface, a Transmit Overhead data Input
Interface Section, a Transmit HDLC Controller, a
Transmit DS3/E3 Framer block and a Transmit LIU In-
terface Block which permits the Terminal Equipment
to transmit data to a remote terminal.
The Receive Sections, consist of a Receive LIU Inter-
face, a Receive DS3/E3 Framer, a Receive HDLC
Controller, a Receive Payload Data Output Interface,
and a Receive Overhead Data Interface which allows
the local terminal equipment to receive data from re-
mote terminal equipment.
The Microprocessor Interface is used to configure the
Framer IC in different operating modes and monitor
the performance of the Framer.
The Performance Monitor Sections consist of a large
number of "Reset-upon-Read" and "Read-Only" reg-
isters that contain cumulative and "one-second" sta-
tistics that reflect the performance/health of the two
channels of the Framer IC/system.
FEATURES
Transmits, Receives and Processes data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.
2 Channel HDLC Controller - Tx and Rx
Interfaces to all Popular Microprocessors
Integrated Framer Performance Monitor
Available in a 160 Pin PQFP package
3.3V Power Supply with 5V Tolerant I/O
Operating Temperature -40°C to +85°C
APPLICATIONS
Network Interface Units
CSU/DSU Equipment.
PCM Test Equipment
Fiber Optic Terminals
DS3/E3 Frame Relay Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT72L52
Reset
TestMode
NibbleLnTF
TxOHEnable
TxOHClk
TxOHFrame
TxAISEn
TxOH
TxOHIns
T3/E3
Transmit
Overhead
Interface
TxLineClk[n:0]
TxPOS[n:0]
TxNEG[n:0]
RxLineClk[n:0]
RxPOS[n:0]
RxNEG[n:0]
ExtLOS
RxOHEnable[n:0]
RxOHClk[n:0]
RxOH[n:0]
RxRed[n:0]
RxOHFrame[n:0]
RxOOF[n:0]
LIU
Interface/
Controller
T3/E3
Receive
Overhead
Interface
Typical Channel n
Where n = 0 or 1
T3/E3 Transmit
Framer
T3/E3
transmit
Input
T3 FEAC & Data
Link Controller
Performance
Monitor
Interrupt
Controller
T3/E3 Receive
Framer
T3/E3
Receive
Output
HDLC
controller
uP
Interface
HDLC
controller
TxOHInd[n:0]
TxNibFrame[n:0]
TxFrame[n:0]
TxNibClk[n:0]
TxLnClk[n:0]
TxFrameRef[n:0]
TxNib[n:0]
TxSer[n:0]
A(11:0)
D(7:0)
ALE_AS
WR_R/W
CS
RDY_DTCK
Reset
INT
MOTO
RD_DS
RxClk[n:0]
RxOHind[n:0]
RxFrame[n:0]
RxNib[n:0]
RxSer[n:0]
RxOUTClk[n:0]
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT72L52 pdf, 반도체, 판매, 대치품
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
áç
PRELIMINARY
TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR IN-
TERFACE IS OPERATING IN THE MOTOROLA MODE ..................................................................................... 44
2.3 INTERFACING THE XRT72L52 DS3/E3 FRAMER TO THE LOCAL µC/µP VIA THE MICROPROCESSOR INTERFACE BLOCK
44
2.3.1 Interfacing the XRT72L52 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus
44
2.3.2 Data Access Modes ................................................................................................................................ 45
Figure 25. Behavior of Microprocessor Interface signals during an Intel-type Programmed I/O Read Oper-
ation ....................................................................................................................................................... 46
Figure 26. Behavior of the Microprocessor Interface Signals, during an Intel-type Programmed I/O Write
Operation ............................................................................................................................................... 47
Figure 27. Illustration of the Behavior of Microprocessor Interface signals, during a Motorola-type Pro-
grammed I/O Read Operation ............................................................................................................... 48
Figure 28. Illustration of the Behavior of the Microprocessor Interface signal, during a Motorola-type Pro-
grammed I/O Write Operation ............................................................................................................... 49
Figure 29. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Intel Type Processor) ................................................................................................................. 50
Figure 30. Behavior of the Microprocessor Interface Signals, during subsequent Read Operations within
the Burst I/O Cycle ................................................................................................................................ 51
Figure 31. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Intel-type Processor) .................................................................................................................. 53
Figure 32. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations within
the Burst I/O Cycle ................................................................................................................................ 54
Figure 33. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Motorola Type Processor) .......................................................................................................... 55
Figure 34. Behavior the Microprocessor Interface Signals, during subsequent Read Operations within the
Burst I/O Cycle (Motorola-type µC/µP) .................................................................................................. 56
Figure 35. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Motorola-type Processor) ........................................................................................................... 57
Figure 36. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations with the
Burst I/O Cycle (Motorola-type µC/µP) .................................................................................................. 58
2.4 ON-CHIP REGISTER ORGANIZATION ...................................................................................................................... 58
2.4.1 Framer Register Addressing .................................................................................................................... 58
TABLE 5: REGISTER ADDRESSING OF THE FRAMER PROGRAMMER REGISTERS ......................................... 59
2.4.2 Framer Register Description .................................................................................................................... 62
PART NUMBER REGISTER (ADDRESS = 0X02) .......................................................................................... 65
VERSION NUMBER REGISTER (ADDRESS = 0X03) ..................................................................................... 65
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ........................................................................ 65
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) ........................................................................ 66
TEST REGISTER (ADDRESS = 0X0C) ....................................................................................................... 67
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ........................................................... 68
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ........................................................................................ 69
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 70
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 71
RXDS3 SYNC DETECT ENABLE REGISTER (ADDRESS = 0X14) ................................................................ 73
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................... 73
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 74
RXDS3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 75
2.4.3 Receive E3 Framer Configuration Registers (ITU-T G.832) .................................................................... 75
RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10) ........................................................... 76
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................... 77
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................... 78
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................... 79
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................... 79
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................... 81
II

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XRT72L52 전자부품, 판매, 대치품
áç
PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) ..................................................................... 128
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 129
TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE (FOR DS3 APPLICATIONS) ........................................... 129
TABLE 11: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.832 APPLICATIONS) ....................... 130
TABLE 12: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.751 APPLICATIONS) ....................... 130
2.7.1 Automatic Reset of Interrupt Enable Bits .............................................................................................. 130
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ...................................................................... 131
2.7.2 One-Second Interrupts .......................................................................................................................... 131
2.8 INTERFACING THE FRAMER TO AN INTEL-TYPE MICROPROCESSOR ........................................................................ 131
TABLE 13: ALTERNATE FUNCTIONS OF PORT 3 PINS ............................................................................. 132
TABLE 14: INTERRUPT SERVICE ROUTINE LOCATION (IN CODE MEMORY) FOR THE INT0* AND INT1* INTERRUPT
INPUT PINS ............................................................................................................................................ 133
Figure 37. Schematic depicting how to interface the XRT72L52 DS3/E3 Framer IC to the 8051 Microcon-
troller ................................................................................................................................................... 133
2.9 INTERFACING THE FRAMER IC TO A MOTOROLA-TYPE MICROPROCESSOR ............................................................ 134
Figure 38. Schematic Depicting how to interface the XRT72L52 DS3/E3 Framer IC to the MC68000 Micro-
processor ............................................................................................................................................ 134
TABLE 15: AUTO-VECTOR TABLE FOR THE MC68000 MICROPROCESSOR .............................................. 135
3.0 The Line Interface and scan section ................................................................................................ 135
Figure 39. Schematic Depicting how to interface the XRT72L52 DS3/E3 Framer IC to the XRT73L02 DS3/
E3/STS-1 LIU IC (one channel shown) ............................................................................................... 136
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE REGISTER .................................................................................. 136
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) ..................................................................... 136
TABLE 16: THE RELATIONSHIP BETWEEN THE STATES OF RLOOP, LLOOP AND THE RESULTING LOOP-BACK MODE
WITH THE XRT7300 DEVICE .................................................................................................................. 138
3.2 BIT-FIELDS WITHIN THE LINE INTERFACE SCAN REGISTER ................................................................................... 138
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ...................................................................... 139
XRT72L52 CONFIGURATION ..................................................................................... 140
4.0 DS3 Operation of the XRT72L52 ...................................................................................................... 140
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 140
4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS .............................................................. 140
Figure 40. DS3 Frame Format for C-bit Parity ................................................................................... 140
Figure 41. DS3 Frame Format for M13 .............................................................................................. 141
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 141
TABLE 17: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 2, (C-BIT PARITY*/M13) WITHIN THE FRAMER OP-
ERATING MODE REGISTER AND THE RESULTING DS3 FRAMING FORMAT ................................................. 142
TABLE 18: C-BIT FUNCTIONS FOR THE C-BIT PARITY DS3 FRAME FORMAT ............................................ 142
4.1.1 Frame Synchronization Bits (Applies to both M13 and C-bit Parity Framing Formats) ......................... 142
4.1.2 Performance Monitoring/Error Detection Bits (Parity) ........................................................................... 143
4.1.3 Alarm and Signaling-Related Overhead Bits ......................................................................................... 143
Valid M-bits, F-bits, and P-bits ........................................................................................ 143
4.1.4 The Data Link Related Overhead Bits ................................................................................................... 144
4.2 THE TRANSMIT SECTION OF THE XRT72L52 (DS3 MODE OPERATION) ............................................................... 144
Figure 42. A Simple Illustration of the Transmit Section, within the XRT72L52, when it has been configured
to operate in the DS3 Mode ................................................................................................................ 145
4.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 145
Figure 43. A Simple Illustration of the Transmit Payload Data Input Interface Block ......................... 146
TABLE 19: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT IN-
TERFACE ............................................................................................................................................... 147
Figure 44. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-
face block (of the XRT72L52) for Mode 1(Serial/Loop-Timing) Operation .......................................... 149
Figure 45. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Interface
block of the XRT72L52 and the Terminal Equipment (for Mode 1 Operation) .................................... 150
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 150
Figure 46. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-
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