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ePV6200 데이터시트 PDF




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기능 VFD Controller
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ePV6200 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ePV6200
VFD Controller
Version 1.2
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03) 5780617




ePV6200 pdf, 반도체, 판매, 대치품
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V. Functional Block Diagram
ePV6200
VFD Controller
DOUT
DIN
CLK
STB
Serial
Data
Interface
OSCI
OSCO
OSC
GPIO9[0:7]
8
GPIOC[0:7]
8
GPIO
MCU
OTP
Data RAM
PLL
Timer
IR
8
8
Segment Driver/
Grid Driver/
High Breakdown
Driver
3
5
4
GR1
GR8
GR9/SG20
GR16/SG13
GR17/SG12/KS12
GR19/SG10/KS10
SG9/KS9
SG5/KS5
SG4/KS4
SG1/KS1
Real Time Clock
/RESET PLLC VDDx3 VSS VEE AVDD
Fig.2a Block diagram
XIN XOUT PLLC
Oscillator
Timing Control
R1(TCC)
WDT
Timer
Prescaler
Data
RAM
Control Sleep
And Wakeup
On I/O port
General
RAM
R4
ROM
Interrupt
Control
Instruction
Register
Instruction
Decoder
Data & Control Bus
R2
R3
R5
STACK
ALU
IOC5
IOC6
IOC7
IOC8
IOC9
IOCC
R5 R6 R7 R8 R9
RC
SPI
Port5
Port6
Port7
Port8
Port9
PortC
(HV)
(HV)
(HV)
(HV)
P54~P57
P60~P67
P70~P77
P80~P87
P90~P97
PC0~PC7
Fig.2b Block diagram
This specification is subject to change without further notice.
04/06/2004 (V1.2)

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ePV6200 전자부품, 판매, 대치품
www.DataSheet4U.com
ePV6200
VFD Controller
VII.2 Operational Register Detail Description
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0
as register actually accesses data pointed by the RAM Select Register (R4).
Example:
Mov A, @0x20
;store a address at R4 for indirect addressing
Mov 0x04, A
Mov A, @0xAA
;write data 0xAA to R20 at bank0 through R0
Mov 0x00, A
R1 (TCC)
TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register).
Written and read by the program as any other register.
R2 (Program Counter)
The structure is depicted in Fig.3.
Generates 4k × 13 external ROM addresses to the relative programming instruction codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
"RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
"MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to "0''.
"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
Fig.3 Program counter organization
R5(PAGE)
CALL and
INTERRUPT
PC A13 A12 A11 A10
0000
0001
0010
0011
A9 A8 A7~A0
PAGE0
0000~03FF
PAGE1
0400~07FF
PAGE2
0800~0BFF
PAGE3
0C00~0FFF
RET
RETL
RETI
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
STACK9
STACK10
STACK11
STACK12
STACK13
STACK14
STACK15
STACK16
store
ACC,R3,R5(PAGE)
restore
"TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change.
The most significant bit (A10~A13) will be loaded with the contents of bit PS0~PS3 in the status register (R5
PAGE 1) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will
store ACC, R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.
R3 (Status, Page selection)
(Status flag, Page selection bits)
7 6 5 43210
RPAGE1 RPAGE0 IOCPAGE T P Z DC C
R/W-0 R/W-0 R/W-0 R R R/W R/W R/W
Bit 0(C) : Carry flag
Bit 1(DC) : Auxiliary carry flag
Bit 2(Z) : Zero flag
Bit 3(P) : Power down bit
This specification is subject to change without further notice.
04/06/2004 (V1.2)

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ePV6200

VFD Controller

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