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PDF XRT86SH221 Data sheet ( Hoja de datos )
| Número de pieza | XRT86SH221 | |
| Descripción | SDH-TO-PDH FRAMER/MAPPER | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT86SH221
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
MAY 2007
REV. P1.0.5
GENERAL DESCRIPTION
The XRT86SH221 (Voyager-Lite) is a physical layer
SDH to PDH mapper/demapper which enables E1
aggregation to STM-1 via standard VC-12 to AU-3
and TUG-3/AU-4 mapping protocols. Voyager-Lite
supports all the framing, mapping and grooming
functions required for STM-1 mapper applications.
The device generates and terminates all SDH
Regenerator Section, Multiplexer Section and Path
Overhead including the low-order Virtual Container
(VC) Path Overhead. E1 framing is transparent;
therefore, the device neither generates nor
terminates the E1 frame.
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM
A single Voyager-Lite performs mapping of 21
asynchronous E1 spans to either VC-12/TU-12/TUG-
2/ VC-3/AU-3/STM-0 or VC-12/TU-12/TUG-2/TUG-3/
STM-0. Mapping to STM-1 requires (3) Voyager-Lite
devices with one acting as "master" framer and two
acting as "slave" framers. In this configuration,
Voyager-Lite performs all the necessary framing,
pointer processing and mapping functions required
for mapping of 63xE1 spans to either VC-12/TU-12/
TUG-2/VC-3/AU-3/STM-1 or VC-12/TU-12/TUG-2/
TUG-3/VC-4/AU-4/STM-1 as shown in the block
diagram.
19.44Mhz
SDH OH
Drop
8kHz
VC-4 POH
Drop
STM-1 SOH
Processor
Master
Slave
Telecom Bus or
Serial Port
Interface
Telecom
Bus
Rx
Telecom
Bus
Tx
SDH
Trans-
Port
Proc
(SOH)
Rx
SDH
Trans-
Port
Proc
(SOH)
Tx
SDH
Path
Proc
(POH)
TU-12
To
TUG2
Rx
VC3/
AU3
TUG3/
VC4/
AU4
Tx
STM-1 SOH
Processor
XRT86SH221 Voyager Lite
VC-12
Mapper
+
TU-12
Pointer
Proc
Rx
VC-12
Cross
Connect
21x21
Rx
VC-12
Mapper
+
TU-12
Pointer
Proc
Tx
VC-12
Cross
Connect
21x21
Tx
21 Ch
E1
Frame
Sync
Bit
Retimer
21 Ch
E1
Short
Haul
LIU
Tx
21 Ch
E1
Short
Haul
LIU
Rx
PLL
E1, 2xE1
4xE1, 8xE1
JTAG
Microprocessor
Egress
Ingress
Recovered
Line Clock
SDH OH
Add
VC-4 P OHSingle Input
Add Clock
Reference
JTAG
Port
Microprocessor
Interface
PRODUCT NUMBER
XRT86SH221IB
PACKAGE ORDERING INFORMATION
PACKAGE TYPE
388 PBGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
PRELIMINARY
XRT86SH221
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
FIGURE 15. TOP LEVEL BLOCK DIAGRAM........................................................................................................................................ 42
4.6 INTERRUPTS AND STATUS ............................................................................................................................ 43
FIGURE 16. INTERRUPT HIERARCHY ............................................................................................................................................... 43
4.7 INTERRUPT PROCESSING AND CONTROL .................................................................................................. 44
4.8 STM-0/1 RECEIVE TRANSPORT PROCESSOR.............................................................................................. 44
FIGURE 17. BYTE_ALIGN BLOCK FUNCTIONAL DIAGRAM .............................................................................................................. 44
TABLE 1: 16-BYTE FRAME FOR TRAIL APID ..................................................................................................................................... 49
FIGURE 18. RECEIVE TRACE BUFFER MEMORY............................................................................................................................... 50
TABLE 2: ADDRESSING SCHEME USED TO ACCESS THE SDH OH BYTES ........................................................................................ 51
FIGURE 19. RECEIVE TRANSPORT OVERHEAD INTERFACE TIMING ................................................................................................... 52
STM-0/1 RECEIVE PATH PROCESSOR................................................................................................. 53
FIGURE 20. POINTER PROCESSING FSM ........................................................................................................................................ 55
TABLE 3: SDH POINTER EVENT TYPES .......................................................................................................................................... 55
FIGURE 21. CONCATENATED POINTER INDICATOR PROCESSING FSM.............................................................................................. 57
TABLE 4: RDI-P SETTINGS AND INTERPRETATION ........................................................................................................................... 58
TABLE 5: STS SIGNAL LABEL MISMATCH DEFECT CONDITIONS ....................................................................................................... 59
TABLE 6: TRUTH TABLE FOR PATH LABEL ERROR CONDITIONS ....................................................................................................... 59
FIGURE 22. PATH OVERHEAD INTERFACE TIMING............................................................................................................................ 62
FIGURE 23. TRANSMIT TRANSPORT OVERHEAD INTERFACE TIMING ................................................................................................. 63
4.9 TELECOM BUS INTERFACE............................................................................................................................ 68
4.9.1 TRANSMIT TELECOM BUS ......................................................................................................................................... 68
FIGURE 24. TRANSMIT TELECOM BUS INTERFACE TIMING................................................................................................................ 68
4.9.2 2KHZ MODE IN STM-1 ................................................................................................................................................. 69
FIGURE 25. C1J1V1 PULSE IN STM-1 2KHZ MODE........................................................................................................................ 69
4.9.3 RECEIVE TELECOM BUS ............................................................................................................................................ 69
FIGURE 26. RECEIVE TELECOM BUS INTERFACE TIMING.................................................................................................................. 69
4.10 VT MAPPER .................................................................................................................................................... 71
FIGURE 27. INTERNAL BUS STRUCTURE ......................................................................................................................................... 71
FIGURE 28. MID BUS INTERFACE.................................................................................................................................................... 73
FIGURE 29. SDH TO VTM DATA TRANSFER WITH ZERO POINTER OFFSET......................................................................................... 73
FIGURE 30. VTM TO SDH DATA TRANSFER .................................................................................................................................... 74
FIGURE 31. E1 INTERFACE TIMING (INTERNAL TO THE CHIP) ........................................................................................................... 75
FIGURE 32. E1 INTERFACE TIMING (E1 SYNCHRONOUS MAPPING, INTERNAL TO THE CHIP)............................................................... 75
TABLE 7: V5 - VT PATH ERROR CHECKING, SIGNAL LABEL AND PATH STATUS ................................................................................ 76
TABLE 8: N2 BYTE STRUCTURE ...................................................................................................................................................... 78
TABLE 9: B7-B8 MULTIFRAME STRUCTURE ....................................................................................................................................... 79
TABLE 10: STRUCTURE OF FRAMES # 73 - 76 OF THE B7-B8 MULTIFRAME ....................................................................................... 79
TABLE 11: K4 (B5-B7) CODING AND INTERPRETATION ...................................................................................................................... 81
TABLE 12: Z7/K4 - VT PATH GROWTH AND VT PATH REMOTE DEFECT INDICATION ........................................................................ 81
FIGURE 33. MKP (MAKE PAYLOAD), ONE OF SEVEN MKG : MAKE VT/TU GROUP ........................................................................... 82
FIGURE 34. MKP (MAKE PAYLOAD), VT/TU GROUP INTERLEAVING................................................................................................. 83
FIGURE 35. MAKE TRIBUTARY (MKT) ............................................................................................................................................. 84
FIGURE 36. EXTRACT PAYLOAD (XTP) ........................................................................................................................................... 85
FIGURE 37. REFERENCE CLOCKS GENERATOR (RCG).................................................................................................................... 86
DATA INTERFACE BETWEEN SDH/FRAMER AND MAPPER .............................................................. 87
FIGURE 38. RECEIVE SDH/FRAMER-ATM INTERFACE ..................................................................................................................... 87
FIGURE 39. TRANSMIT SDH/FRAMERMAPPER INTERFACE ............................................................................................................... 87
FIGURE 40. E1 FRAMER SYNCHRONIZATION FLOW DIAGRAM .......................................................................................................... 88
FIGURE 41. FLOW OF CRC-4 MULTIFRAME ALIGNMENT FOR INTERWORKING .................................................................................... 90
4.11 E1 PHY LOOPBACK DIAGNOSTICS ............................................................................................................. 93
4.11.1 E1 LOOPBACKS......................................................................................................................................................... 93
FIGURE 42. E1 FACILITY LOOPBACK............................................................................................................................................... 93
4.11.2 E1 FACILITY I/O LOOPBACK .................................................................................................................................... 94
FIGURE 43. E1 FACILITY I/O LOOPBACK ......................................................................................................................................... 94
4.11.3 E1 MODULE LOOPBACK ......................................................................................................................................... 95
FIGURE 44. E1 MODULE LOOPBACK................................................................................................................................................ 95
4.11.4 ALARM AND AUTO AIS ............................................................................................................................................. 96
FIGURE 45. E1 AUTO AIS INSERTION ............................................................................................................................................. 96
TABLE 13: E1 TO STM-0 - RESPONSE TIME < 125 US ..................................................................................................................... 96
TABLE 14: STM-0 TO E1 - RESPONSE TIME < 125 USEC ................................................................................................................. 96
5.0 ANALOG FRONT END / LINE INTERFACE UNIT (LIU) SECTION...................................................... 98
FIGURE 46. SIMPLIFIED BLOCK DIAGRAM OF THE LIU SECTION ....................................................................................................... 98
5.1 TRANSMIT LINE INTERFACE UNIT................................................................................................................. 99
5.1.1 JITTER ATTENUATOR................................................................................................................................................. 99
5.1.2 TAOS (TRANSMIT ALL ONES).................................................................................................................................... 99
II
5 Page 
PRELIMINARY
XRT86SH221
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
8.1 STM-0/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION .......................................................... 317
8.2 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-0 APPLICATIONS ............... 317
FIGURE 63. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STM-0/STM-1 TELECOM BUS
INTERFACE (FOR STM-0 APPLICATIONS) ...................................................................................................................... 317
TABLE 284 TIMING INFORMATION FOR THE TRANSMIT STM-0 TELECOM BUS INTERFACE - STM-0 APPLICATIONS ........................... 318
8.3 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 SLOT MASTER APPLICATIONS
318
FIGURE 64. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STM-0/STM-1 TELECOM BUS
INTERFACE (FOR STM-1 APPLICATIONS) ...................................................................................................................... 318
FIGURE 65. AN ILLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE TXSBFP_IN_OUT OUTPUT PIN, AND THE TXA_CLK OUTPUT
PIN, WITHIN THE TRANSMIT STM-1 TELECOM BUS INTERFACE (SLOT MASTER MODE APPLICATION) ............................... 319
TABLE 285 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE - STM-1 SLOT MASTER APPLICATIONS
319
8.4 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 SLOT SLAVE APPLICATIONS
320
FIGURE 66. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STM-0/STM-1 TELECOM BUS
INTERFACE (FOR STM-1 APPLICATIONS) ...................................................................................................................... 320
FIGURE 67. AN ILLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE TXSBFP INPUT PIN AND THE TXA_CLK OUTPUT PIN WITHIN THE
TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE (STM-1 SLOT SLAVE APPLICATIONS) ........................................... 320
TABLE 286 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE - STM-1 SLOT SLAVE APPLICATIONS 321
8.5 THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-0 APPLICATIONS.................. 321
FIGURE 68. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE INPUT VIA THE RECEIVE STM-0/STM-1 TELECOM BUS IN-
TERFACE ..................................................................................................................................................................... 321
TABLE 287 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE - STM-0 APPLICATIONS ................. 321
8.6 THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 APPLICATIONS.................. 322
FIGURE 69. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE INPUT VIA THE RECEIVE STM-0/STM-1 TELECOM BUS IN-
TERFACE ..................................................................................................................................................................... 322
TABLE 288 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE - STM-1 APPLICATIONS ................. 322
8.7 STM-0 LIU INTERFACE TIMING INFORMATION .......................................................................................... 323
8.7.1 RECEIVE STM-0/STM-1 LIU INTERFACE TIMING.................................................................................................... 323
FIGURE 70. AN ILLUSTRATION OF THE WAVEFORMS OF THE RECEIVE STM-0/STM-1 SIGNALS THAT ARE INPUT TO THE RECEIVE STM-0/
STM-1 LIU INTERFACE BLOCK - SHARED PORT ........................................................................................................... 323
TABLE 289 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 LIU INTERFACE WHEN THE RECEIVE STM-0/STM-1 TOH PROCESSOR
BLOCK HAS BEEN CONFIGURED TO SAMPLE THE RXSTM0DATA SIGNAL UPON THE RISING EDGE OF THE RXSTM0CLK SIGNAL
323
8.7.2 TRANSMIT STM-0/STM-1 LIU INTERFACE TIMING................................................................................................. 324
FIGURE 71. AN ILLUSTRATION OF THE WAVEFORMS OF THE STM-0/STM-1 SIGNALS THAT ARE OUTPUT FROM THE TRANSMIT STM-0/STM-
1 LIU INTERFACE - DEDICATED PORT........................................................................................................................... 324
TABLE 290 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 LIU INTERFACE WHEN THE TRANSMIT STM-0/STM-1 TOH PROCES-
SOR BLOCK HAS BEEN CONFIGURED TO UPDATE THE TXSTM0DATA SIGNAL UPON THE RISING EDGE OF THE TXSTM0CLK SIGNAL
324
8.8 TRANSMIT STM-0/STM-1 TOH AND POH DATA INPUT PORT ................................................................... 325
FIGURE 72. ILLUSTRATION OF TIMING WAVE-FORM OF THE TRANSMIT STM-0/STM-1 TOH AND POH OVERHEAD DATA INPUT PORT 325
TABLE 291 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 TOH AND POH OVERHEAD DATA INPUT PORT ..................... 325
8.9 TRANSMIT VC-4 POH DATA INPUT PORT ................................................................................................... 326
FIGURE 73. ILLUSTRATION OF TIMING WAVE-FORM OF THE TRANSMIT VC-4 POH DATA INPUT PORT ............................................. 326
TABLE 292 TIMING INFORMATION FOR THE TRANSMIT VC-4 POH DATA INPUT PORT ..................................................................... 326
8.10 RECEIVE STM-0/STM-1 TOH AND POH DATA OUTPUT PORT ................................................................ 327
FIGURE 74. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE RECEIVE STM-0/STM-1 TOH AND POH DATA OUTPUT PORT...... 327
TABLE 293 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 TOH AND POH DATA OUTPUT PORT ..................................... 327
8.11 RECEIVE VC-4 POH DATA OUTPUT PORT ................................................................................................ 328
FIGURE 75. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE RECEIVE VC-4 POH DATA OUTPUT PORT..................................... 328
TABLE 294 TIMING INFORMATION FOR THE RECEIVE VC-4 POH DATA OUTPUT PORT ................................................................... 328
8.12 INGRESS DIRECTION - ADD/DROP PORT TIMING.................................................................................... 329
8.12.1 INGRESS DIRECTION - ADD PORT TIMING .......................................................................................................... 329
FIGURE 76. ILLUSTRATION OF THE INGRESS-DIRECTION ADD PORT SIGNALS ................................................................................ 329
TABLE 295 TIMING INFORMATION FOR THE INGRESS-DIRECTION ADD PORT SIGNALS ..................................................................... 329
8.12.2 INGRESS DIRECTION - DROP PORT TIMING........................................................................................................ 330
FIGURE 77. ILLUSTRATION OF THE INGRESS-DIRECTION DROP PORT SIGNALS ............................................................................... 330
TABLE 296 TIMING INFORMATION FOR THE INGRESS-DIRECTION DROP PORT SIGNALS ................................................................... 330
8.13 EGRESS DIRECTION - ADD/DROP PORT TIMING..................................................................................... 331
8.13.1 EGRESS DIRECTION - ADD PORT TIMING............................................................................................................ 331
FIGURE 78. ILLUSTRATION OF THE EGRESS-DIRECTION ADD PORT SIGNALS ................................................................................. 331
TABLE 297 TIMING INFORMATION FOR THE EGRESS-DIRECTION ADD PORT SIGNALS ...................................................................... 331
8.13.2 EGRESS DIRECTION - DROP PORT TIMING ......................................................................................................... 332
VIII
11 Page | ||
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| PDF Descargar | [ Datasheet XRT86SH221.PDF ] | |
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