DS3100 Datasheet PDF - Maxim Integrated Products
| Part Number | DS3100 | |
| Description | Stratum 3/3E Timing Card IC | |
| Manufacturers | Maxim Integrated Products | |
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GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3100 is a complete central timing and
synchronization solution for SONET/SDH network
elements. With two multiprotocol BITS/SSU receivers
and 14 input clocks, the device directly accepts both
external timing and line timing from a large number of
line cards. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the Stratum 3
and 3E requirements of GR1244, GR-253, and the
requirements of G.812 Type III and G.813. From the
output of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3100 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3100 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs.
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
TIMING FROM
LINE CARDS
(VARIOUS RATES) 14
TIMING FROM
BITS/SSU
(DS1, E1, CC, ETC.) 2
LOCAL TCXO
OR OCXO
DS3100 2
SONET/SDH
SYNCHRONIZATION
IC
11
TIMING TO BITS/SSU
(DS1, E1, CC, ETC.)
TIMING TO
LINE CARDS
(VARIOUS RATES)
CONTROL STATUS
DS3100
Stratum 3/3E Timing Card IC
FEATURES
Synchronization Subsystem for Stratum 3E, 3,
4E and 4, SMC and SEC
- Meets Requirements of GR-1244 Stratum 3/3E,
GR-253, G.812 Types I, III and IV, and G.813
- Stratum 3E Holdover Accuracy with Suitable
External Oscillator
- Programmable Bandwidth, 0.5mHz to 70Hz
- Hitless Reference Switching on Loss of Input
- Phase Build-Out and Transient Absorption
- Locks to and Generates 125MHz for Gigabit
Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
- 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
- Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
- Two 64kHz Composite Clock Receivers
- Continuous Input Clock Quality Monitoring
- Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
- Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
- Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
- One 64kHz Composite Clock Transmitter
- One 1.544MHz/2.048MHz Output Clock
- Two Sync Pulses: 8kHz and 2kHz
- Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
Two Multiprotocol BITS/SSU Transceivers
- Receive and Transmit DS1, E1, 2048kHz, and
6312kHz Timing Signals
- Insert and Extract SSM Messages (DS1, E1)
- Automatically Invalidate Clocks on LOS, OOF,
AIS, and Other Defects
Internal Compensation for Master Clock
Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
ORDERING INFORMATION
PART
TEMP RANGE
DS3100GN -40°C to +85°C
DS3100GN+ -40°C to +85°C
+Denotes a lead-free package.
PIN-PACKAGE
256 CSBGA (17mm) 2
256 CSBGA (17mm) 2
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 060607
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DS3100 Stratum 3/3E Timing Card IC
LIST OF FIGURES
Figure 2-1. DS3100 Block Diagram ............................................................................................................................. 8
Figure 3-1. Typical Application Example ..................................................................................................................... 9
Figure 7-1. T0 DPLL State Transition Diagram ......................................................................................................... 34
Figure 7-2. T4 DPLL State Transition Diagram ......................................................................................................... 37
Figure 7-3. Typical MTIE for T0 DPLL Output ........................................................................................................... 43
Figure 7-4. Typical TDEV for T0 DPLL Output .......................................................................................................... 44
Figure 7-5. DPLL Block Diagram ............................................................................................................................... 46
Figure 7-6. OC10 8kHz Options ................................................................................................................................ 54
Figure 7-7. BITS Transceiver Block Diagram ............................................................................................................ 58
Figure 7-8. BITS Transceiver Master Clock PLL Block Diagram .............................................................................. 59
Figure 7-9. BITS Transmitter Clock Mux Block Diagram........................................................................................... 60
Figure 7-10. BITS Transceiver External Components............................................................................................... 62
Figure 7-11. Jitter Tolerance, DS1 Mode .................................................................................................................. 63
Figure 7-12. Jitter Tolerance, E1 and 2048kHz Modes ............................................................................................. 64
Figure 7-13. Transmit Pulse Template, DS1 Mode ................................................................................................... 66
Figure 7-14. Transmit Pulse Template, E1 Mode...................................................................................................... 66
Figure 7-15. Transmit Pulse Template, 2048kHz Mode ............................................................................................ 67
Figure 7-16. FAS/Si/RAI/Sa Source Logic................................................................................................................. 72
Figure 7-17. GR-378 Composite Clock Pulse Mask.................................................................................................. 76
Figure 7-18. SPI Clock Polarity and Phase Options.................................................................................................. 78
Figure 7-19. SPI Bus Transactions............................................................................................................................ 79
Figure 9-1. JTAG Block Diagram............................................................................................................................. 198
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 200
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 204
Figure 10-2. Recommended Termination for LVPECL Pins.................................................................................... 205
Figure 10-3. Recommended External Components for AMI Composite Clock Pins ............................................... 206
Figure 10-4. BITS Receiver Timing Diagram........................................................................................................... 208
Figure 10-5. BITS Transmitter Timing Diagram....................................................................................................... 209
Figure 10-6. Parallel Interface Timing Diagram (Nonmultiplexed) .......................................................................... 211
Figure 10-7. Parallel Interface Timing Diagram (Multiplexed) ................................................................................. 212
Figure 10-8. SPI Interface Timing Diagram ............................................................................................................. 213
Figure 10-9. JTAG Timing Diagram......................................................................................................................... 214
Figure 11-1. DS3100 Pin Assignment—Left Half .................................................................................................... 219
Figure 11-2. DS3100 Pin Assignment—Right Half.................................................................................................. 220
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