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PDF 54VCXH162245 Data sheet ( Hoja de datos )
| Número de pieza | 54VCXH162245 | |
| Descripción | Rad hard low voltage CMOS 16-bit bus buffer transceiver | |
| Fabricantes | STMicroelectronics | |
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54VCXH162245
Rad hard low voltage CMOS 16-bit bus buffer transceiver
(3-state) with 3.6V tolerant inputs and outputs
Features
■ 1.65 to 3.6V inputs and outputs
■ High speed A outputs:
– tPD = 3.4ns at VCC = 3.0 to 3.6V
– tPD = 4.3ns at VCC = 2.3 to 2.7V
■ Symmetrical impedance A output:
– |IOH| = IOL = 12mA (Min) at VCC = 3.0V
– |IOH| = IOL = 8mA (Min) at VCC = 2.3V
■ High speed B outputs:
– tPD = 2.5ns (Max) at VCC = 3.0 to 3.6V
– tPD = 3.2ns (Max) at VCC = 2.3 to 2.7V
■ Symmetrical impedance A output:
– |IOH| = IOL = 24mA (Min) at VCC = 3.0V
– |IOH| = IOL = 18mA (Min) at VCC = 2.3V
■ Power down protection on inputs and outputs
■ 26Ω serie resistors in A port output
■ Operating voltage range:
– VCC(Opr) = 1.65V to 3.6V
■ Pin and function compatible with 54 SERIES
H162245
■ Bus hold provided on both sides
■ Cold spare function
■ Latch-up performance exceeds
300mA (JESD 17)
■ ESD performance:
– HBM > 2000V
(MIL STD 883 method 3015); MM > 200V
■ 300KRad Mil1019.6 Condition A, (RHA QML
qualification extension undergone)
■ No SEL, no SEU under 72 Mev/cm2/mg LET
heavy ions irradiation
■ QML qualified product
■ Device fully compliant with
DSCC SMD 5962-02508
Flat-48
Description
The 54VCXH162245 is a low voltage CMOS 16
bit bus transceiver (3-state) fabricated with sub-
micron silicon gate and five-layer metal wiring
C2MOS technology. It is ideal for low power and
very high speed 1.65 to 3.6V applications; it can
be interfaced to 3.6V signal environment for both
inputs and outputs.
This IC is intended for two-way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The two enable inputs nG can be used to disable
the device so that the buses are effectively
isolated. The device circuits is including 26Ω
series resistance in the A port outputs. These
resistors permit to reduce line noise in high speed
applications. Bus hold on data inputs is provided
in order to eliminate the need for external pull-up
or pull-down resistor.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage. All floating bus terminals during High Z
State must be held HIGH or LOW.
July 2007
Rev 6
1/18
www.st.com
18
1 page  
54VCXH162245
2.2 Pin description
Table 1. Pin description
Pin N°
1
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
24
25
36, 35, 33, 32, 30, 29, 27, 26
47, 46, 44, 43, 41, 40, 38, 38
48
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
Pin settings
Symbol
1DIR
1B1 to 1B8
2B1 to 2B8
2DIR
2G
2A1 to 2A8
1A1 to 1A8
1G
GND
VCC
Name and function
Directional control
Data Inputs/Outputs
Data Inputs/Outputs
Directional Control
Output enable input
Data Inputs/Outputs
Data Inputs/Outputs
Output Enable Input
Ground (0V)
Positive supply voltage
2.3
Note:
Truth table
Table 2. Truth table
Inputs
G
L
L
H
DIR
L
H
X
X = Do not care; Z = High Impedance
Function
A BUS
B BUS
OUTPUT
INPUT
INPUT
OUTPUT
ZZ
Output
Yn
A=B
B=A
Z
5/18
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54VCXH162245
Electrical characteristics
Table 8. AC electrical characteristics (CL = 30pF, RL = 500Ω, Input tr = tf = 2.0ns)
Test condition
Value
Symbol
Parameter
VCC
-55 to 125 °C
Unit
(V) Min Max
tPLH tPHL Propagation delay
time (A to B)
2.3 to 2.7
3.0 to 3.6
1.0 4.0 ns
0.8 3.6
tPLH tPHL Propagation delay
time (B to A)
2.3 to 2.7
3.0 to 3.6
1.0 4.9 ns
0.8 4.0
tPZL tPZH Output enable time
(A to B)
2.3 to 2.7
3.0 to 3.6
1.0 5.8 ns
0.8 4.3
tPZL tPZH Output enable time
(B to A)
2.3 to 2.7
3.0 to 3.6
1.0 6.8 ns
0.8 4.8
tPLZ tPHZ Output disable time
(A to B)
2.3 to 2.7
3.0 to 3.6
1.0 4.8 ns
0.8 5.6
tPLZ tPHZ Output disable time (B
to A)
2.3 to 2.7
3.0 to 3.6
1.0 5.7 ns
0.8 7.0
tOSLH tOSHL
Output to output skew
time (1) (2)
2.3 to 2.7
3.0 to 3.6
0.5
ns
0.5
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|,
tOSHL = | tPHLm - tPHLn|)
2. Parameter guaranteed by design
Table 9. Capacitive characteristics
Test condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min Typ Max
Unit
CIN Input capacitance
2.5 or 3.3 VIN = 0 or VCC
4
pF
COUT Output capacitance
2.5 or 3.3 VIN = 0 or VCC
8
pF
Power dissipation
CPD capacitance (1)
2.5 or 3.3
fIN = 10MHz
VIN = 0 or VCC
28
pF
1. CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the
operating current consumption without load. (Refer to Test Circuit). Average operating current can be
obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit)
11/18
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 54VCXH162245.PDF ] | |
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