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부품번호 AD392 기능
기능 Complete Quad 12-Bit D/A Converter
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AD392 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ANALOG
W DEVICES
CompleteQuad12-Bit
OfAConvertewr ithReadback
FEATURES
Data Readback Capability
Four Complete, Voltage Output, 12-Bit DACs in One
32-Pin Hermetic Package
Fast Bus Access: 40ns max, Tmin-Tmax
Asynchronous Reset to Zero Volts
Minimum of Two TTL Load Drive (Readback Mode)
Double-Buffered Data Latches
Monotonicity Guaranteed TminoTmax
Linearity Error :t:1/2LSB
Low Digital-to-Analog Feedthrough, 2nV sec typ
Factory Trimmed Gain and Offset
Low Cost
OBPRODUCT DESCRIPTION
SThe AD392 is a quad I2-bit, high-speed, voltage output digital-to-
Oanalog converter with readback in a 32-pin hermetically sealed
package. The design is based on a custom IC interface to complete
LI2-bit DAC chips which reduces chip count and provides high
reliability. The AD392 is ideal for systems requiring digital
Econtrol of many analog voltages and for the monitoring of these
Tanalog voltages especially where board space is a premium. Such
Eapplications include ATE, robotics, process controllers and
PRODUCT HIGHLIGHTS
1. The AD392 is packaged in a 32-pin DIP and is a complete
solution to space constraint multiple DAC applications.
2. Readback capability provides system monitor of DAC output
useful in ATE, robotics or any closed-loop system.
3. Fast bus access time of 40ns maximum allows for fast system
updating compatible with high-speed microprocessing.
4. Simultaneous reset to zero volts output is extremely useful
precision fIlters.
for system calibration or simply when all DAC outputs must
Featuring maximum access time of 40ns, the AD392 is capable
initially start at zero volts.
of interfacing to the fastest of microprocessors. The readback
capability provides a diagnostic check between the data sent
5. Readback drive capability of two TTL loads virtually eliminates
the need to buffer.
from the microprocessor and the actual data received and trans-
ferred to the DAC. When RESET is low, all four DACs are
simultaneously set to (bipolar) zero providing a known starting
6. Each DAC is independently addressable, providing a versatile
control architecture for simple interface to microprocessors.
point.
7. Monolithic DAC chips provide excellent linearity and guaran-
The AD392 is laser-trimmed to :!:1/2LSB integral linearity and
teed monotonicity over the full operating temperature range.
:!:ILSB max differential linearity at + 25°C. Monotonicity is
guaranteed over the full operating temperature range. The high
initial accuracy and stability over temperature are made possible
by the use of precision thin-fIlm resistors.
The individual DAC registers are accessed by the address lines
AO and Al and control lines CS and 2ND UP. These control
8. Low digital-to-analog feedthrough (2nV sec typ) is maintained
to assure DAC accuracy.
9. New pin stake package provides a low-cost solution to cost
constraint applications.
signals permit the registers of the four DACs to be loaded
sequentially and the outputs to be simultaneously updated.
The AD392 outputs are calibrated for a :!:lOV output range
with positive true offset binary input coding.
The AD392 is packaged in a 32-lead ceramic package and is
hermetically sealed. The AD392 is specified for operation over
the 0 to + 70°C temperature range.
Information furnished by Analog Devices is believed to be accurate
and reliable. However. no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106
Tel: 617/329-4700
TWX:710/394-6577
West Coast
Mid-West
Texas
714/641-9391
3121350-9399
2141231-5094




AD392 pdf, 반도체, 판매, 대치품
Theoryof Operation
The AD392 is a quad 12-bit digital-to-analog converter with
DA1;A AND CONTROL SIGNAL FORMAT
readback capability. The analog portion of the AD392 includes
four bipolar process digital-to-analog converters. Each DAC
contains current steering switches and a resistor ladder network
which is laser-wafer trimmed for 12-bit accuracy. A precision
output amplifier for voltage out operation and an internal highly
stable voltage reference are all integrated on a single chip. The
The double buffered registers of the AD392 are addressed by
the CS, Al and AO lines. Each rank of registers is 12 bits wide
and is presented in a straight offset binary notation. The first
rank of registers are loaded sequentially, with valid CS, AI, AO
on the trailing rising edge of WR. The second rank of registers,
on the other hand, are loaded simultaneously with the data
DAC is fIXed to run in bipolar, 20V span analog output mode as which is in their corresponding first rank registers, with a valid
shown in Table I.
CS and positive pulse of the 2ND UP command. (Note: All
Data Input
I AnalogOutput
AnalogOutput Vollage
second rank registers can be made transparent by tieing the
2ND UP line to a Logic "1".) The data loaded into the second
rank registers represents the actual digital code which is on the
1111 1111 1111 I + I,(VREFIN){220O4487} +9.995IV + Full Scale-ILSB
input of the individual DACs. This data can be read back through
the data port, with valid CS, Al and AO, by taking the RD line
I1100 0000 0000 I + I,(VREFIN) { 210O4824} .+5.000V
+ 1/2Scale
to a Logic "0". The AD392 also features an asyncronous reset
to zero volts for all four DACs by applying a negative pulse to
1000 0000 0001
I +I,(VREFIN) {28}
I +4.88mV
1000 0000 0000
1 +I,(VREFIN ){28}
I +o.ooov
0111 1111 llli I -I'(VREFIN) {-2L0}48 I -4.88mV
OB0100 0000 0000 I -I'(VREFIN) {2-10O4284} I - 5.000V
S0000 0000
-I'(VREFIN) g}
I -IO.OOOV
+ILSB
Zero
-ILSB
- 1/2Scale
- FullScale
OTable I. AD392 Bipolar Code Table.
LThe digital portion of the AD392 includes the readback function,
Ucontrol logic and registers all integrated on a custom IC. Data
Ecan be latched into anyone of the first rank registers by selecting
U Tthe correct combination of address lines (AOand AI) and CS.
EThe second rank registers are controlled by the 2ND UP control
the RESET line. Executing a reset replaces the contents of both
ranks of registers with the bipolar zero code (MSB equals Logic
"1", all other bits equal Logic "0".)
CS Al
IX
XX
0X
0X
00
00
00
00
AO WR
XX
XX
RD
X
X
XX X
XX X
0I
0
0I
II
0
II
RESET
I
0
I
I
I
I
I
I
2ND Up
X
X
Output
Chip ReadlWrite Disable
MSBs Go to I,All
OthersGotoO
I All 2ND Rank
Latches Transparent
0 All 2ND Rank
Latches Latched
X ReadBackDACI
2ND Rank
X Write to 1ST Rank
DACI
X Read Back DAC2
2ND Rank
X Write to 1ST Rank
line. Use of the 2ND UP line enables the DACs to be updated
DAC2
simultaneously. The digital word can be readback from the
0I0I
0
I
X ReadBackDAC3
second rank registers by asserting the correct address lines,
2ND UP and RD command. The RD and WR commands
0 I0
II
2ND Rank
X Write to 1ST Rank
control the bidirectional I/O port. The AD392 features a RESET
command for simultaneous update of all DACs to 0 volts out.
This is useful for easy system calibration.
0 I I I 0'
0 I I ru- I
I
I
DAC3
X ReadBackDAC4
2ND Rank
X Write to 1ST Rank
DAC4
AD392
Symbols: X = Don'tCare
I = Logic High
0 = Logic Low
U = Positive Trailing Edge Triggered
Table II. AD392 Truth Table
CD
!!!1
.0..
eIn
I
u((0''))
<i.
en
::i
~
c
~z
aQ:.
WR AD 2NDUP
+5V DGND
Figure 1. AD392Block Diagram
-4-
--

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